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ORCIDRaghavendra B. Deshmukh
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- affiliation: VNIT Nagpur, India
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2020 – today
- 2022
[j8]Pravin Zode
, Raghavendra B. Deshmukh:
Optimization of elliptic curve scalar multiplication using constraint based scheduling. J. Parallel Distributed Comput. 167: 232-239 (2022)- 2021
- [j7]Pravin Zode, Raghavendra B. Deshmukh:
Novel fault attack resistant architecture for elliptic curve cryptography. Microprocess. Microsystems 84: 104049 (2021) - 2020
- [j6]Meenu Rani, Sanjay B. Dhok, Raghavendra B. Deshmukh, Punit Kumar:
Overlap Aware Compressed Signal Classification. IEEE Access 8: 52950-52967 (2020) - [j5]Meenu Rani, Sanjay B. Dhok, Raghavendra B. Deshmukh:
A Machine Condition Monitoring Framework Using Compressed Signal Processing. Sensors 20(1): 319 (2020)
2010 – 2019
- 2018
- [j4]Meenu Rani, Sanjay B. Dhok, R. B. Deshmukh:
A Systematic Review of Compressive Sensing: Concepts, Implementations and Applications. IEEE Access 6: 4875-4894 (2018) - [j3]Pankaj U. Joshi, Raghavendra B. Deshmukh, Venkateshwarlu Gudur:
Self-compensation scheme for truncation error in fixed width multipliers. IET Circuits Devices Syst. 12(1): 55-62 (2018) - [c11]Vineysarathi Kokkula, Akash Joshi, Raghavendra B. Deshmukh:
Supply and Temperature Independent Voltage Reference Circuit in Subthreshold Region. VDAT 2018: 109-120 - [c10]Khuushi, Vanadana Jain, Rajendra M. Patrikar, Raghavendra B. Deshmukh:
Real Time Mixing Index Measurement of Microchannels Using OpenCV. VDAT 2018: 278-284 - [c9]Saket Thool, Raghavendra B. Deshmukh, Rajendra M. Patrikar:
Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT Applications. VDAT 2018: 705-719 - 2017
- [c8]Pravin Zode, Raghavendra B. Deshmukh, Abdus Samad:
Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm. VDAT 2017: 48-55 - 2016
- [j2]Anita Arvind Deshmukh, Raghavendra B. Deshmukh:
Design of resolution/power controllable Asynchronous Sigma-Delta Modulator. EURASIP J. Adv. Signal Process. 2016: 105 (2016) - [c7]Bharti Navlani, Pankaj U. Joshi, Raghavendra B. Deshmukh:
Data dependent spurious power reduction for fixed width multiplier. VDAT 2016: 1-2 - 2015
- [c6]Pravin Zode, Raghavendra B. Deshmukh:
Side channel attack resistant architecture for elliptic curve cryptography. VDAT 2015: 1-2 - 2013
- [c5]Shrirang Korde, Amol Khandare, Raghavendra B. Deshmukh, Rajendra M. Patrikar:
Computational Functions' VLSI Implementation for Compressed Sensing. VDAT 2013: 35-43 - 2011
- [c4]Aniruddha Kanhe, Bibhudendra Acharya, R. B. Deshmukh:
Design and Implementation of the Low Power 0.64mW, 380 KHz Continuous Time Sigma Delta ADC. ICETET 2011: 280-283 - [c3]Anita Arvind Deshmukh, Raghavendra B. Deshmukh, Rajendra M. Patrikar:
Low Power Asynchronous Sigma-Delta Modulator Using Hysteresis Level Control. ISVLSI 2011: 353-354
2000 – 2009
- 2009
- [j1]Rahul M. Badghare, Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rajendra M. Patrikar:
Design of Low Power Parallel Multiplier. J. Low Power Electron. 5(1): 31-39 (2009) - 2007
- [c2]Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, Rajendra M. Patrikar:
FPGA Implementation of Low Power Parallel Multiplier. VLSI Design 2007: 115-120 - 2006
- [c1]Shantanu A. Bhalerao, Abhishek V. Chaudhary, Raghavendra B. Deshmukh, Rajendra M. Patrikar:
Powering Wireless Sensor Nodes using Ambient RF Energy. SMC 2006: 2695-2700
Coauthor Index
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