BibTeX records: Ivailo M. Nedelchev

• > Home > Ivailo M. Nedelchev

@inproceedings{DBLP:conf/iccd/ChenN97,
  author    = {Benjamin Chen and
               Ivailo M. Nedelchev},
  title     = {Power Compiler: {A} Gate-Level Power Optimization and Synthesis System},
  booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI}
               in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
               October 12-15, 1997},
  pages     = {74--79},
  publisher = {{IEEE} Computer Society},
  year      = {1997},
  url       = {https://doi.org/10.1109/ICCD.1997.628852},
  doi       = {10.1109/ICCD.1997.628852},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/conf/iccd/ChenN97.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@phdthesis{DBLP:phd/ethos/Nedelchev95,
  author    = {Ivailo M. Nedelchev},
  title     = {Asynchronous {VLSI} design},
  school    = {University of Surrey, Guildford, {UK}},
  year      = {1995},
  url       = {http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308795},
  timestamp = {Fri, 30 Sep 2016 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/phd/ethos/Nedelchev95.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/YantchevHJN95,
  author    = {Jelio Todorov Yantchev and
               C. G. Huang and
               Mark B. Josephs and
               Ivailo M. Nedelchev},
  title     = {Low-latency asynchronous {FIFO} buffers},
  booktitle = {Second Working Conference on Asynchronous Design Methodologies, May
               30-31, 1995, London, England, {UK}},
  pages     = {24--31},
  publisher = {{IEEE} Computer Society},
  year      = {1995},
  url       = {https://doi.org/10.1109/WCADM.1995.514639},
  doi       = {10.1109/WCADM.1995.514639},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/conf/async/YantchevHJN95.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dimacs/JesshopeN94,
  author    = {Chris R. Jesshope and
               Ivailo M. Nedelchev},
  editor    = {D. Frank Hsu and
               Arnold L. Rosenberg and
               Dominique Sotteau},
  title     = {Asynchronous packet routers},
  booktitle = {Workshop on Interconnection Networks and Mapping and Scheduling Parallel
               Computations, Proceedings of a {DIMACS} Workshop, Piscataway, New
               Jersey, USA, February 7-9, 1994},
  series    = {{DIMACS} Series in Discrete Mathematics and Theoretical Computer Science},
  volume    = {21},
  pages     = {211--227},
  publisher = {{DIMACS/AMS}},
  year      = {1994},
  url       = {https://doi.org/10.1090/dimacs/021/15},
  doi       = {10.1090/dimacs/021/15},
  timestamp = {Tue, 16 Jul 2019 17:45:06 +0200},
  biburl    = {https://dblp.org/rec/conf/dimacs/JesshopeN94.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/glvlsi/NedelchevJ94,
  author    = {Ivailo M. Nedelchev and
               Chris R. Jesshope},
  title     = {Basic building blocks for asynchronous packet routers},
  booktitle = {Fourth Great Lakes Symposium on Design Automation of High Performance
               {VLSI} Systems, {GLSV} '94, Notre Dame, IN, USA, March 4-5, 1994},
  pages     = {184--187},
  publisher = {{IEEE}},
  year      = {1994},
  url       = {https://doi.org/10.1109/GLSV.1994.289972},
  doi       = {10.1109/GLSV.1994.289972},
  timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
  biburl    = {https://dblp.org/rec/conf/glvlsi/NedelchevJ94.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}