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ORCIDZbigniew Jaworski
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2010 – 2019
- 2019
[c7]Zbigniew Jaworski
:
Highly Linear 4-bit Flash ADC Implemented in 22 nm FD-SOI Process. MIXDES 2019: 221-226- 2018
- [c6]Zbigniew Jaworski:
High Resolution Latched Comparator Implemented in 22 nm FD-SOI Process. MIXDES 2018: 149-153 - 2017
- [c5]Zbigniew Jaworski:
A highly linear 4-bit DAC with 1 GHz sampling rate implemented in 28 nm FD-SOI process. MIXDES 2017: 189-195 - 2016
- [c4]Zbigniew Jaworski:
Verilog HDL model based thermometer-to-binary encoder with bubble error correction. MIXDES 2016: 249-254 - 2015
- [c3]Zbigniew Jaworski:
Choosing the optimal HDL model of thermometer-to-binary encoder. MIXDES 2015: 297-300 - [c2]Zbigniew Jaworski:
Optimization of capacitive divider for 8-bit DAC realized in 65 nm CMOS process. MIXDES 2015: 364-369 - 2014
- [j3]András Bárdossy, Aleksandra Blinowska, Wieslaw Kuzmicz, Jacky Ollitrault, Michal Lewandowski, Andrzej Przybylski, Zbigniew Jaworski:
Fuzzy logic-based diagnostic algorithm for implantable cardioverter defibrillators. Artif. Intell. Medicine 60(2): 113-121 (2014)
2000 – 2009
- 2004
- [j2]Adam Wojtasik, Zbigniew Jaworski, Wieslaw Kuzmicz, Andrzej Wielgus, Andrzej Walkanis, Dariusz Sarna:
Fuzzy logic controller for rate-adaptive heart pacemaker. Appl. Soft Comput. 4(3): 259-270 (2004)
1990 – 1999
- 1997
- [c1]Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz:
Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation. VTS 1997: 172-176 - 1996
- [j1]Zbigniew Jaworski, Mariusz Niewczas, Miroslaw Grygolec, Wieslaw Kuzmicz:
Architecture of a testable analog fuzzy logic controller. IEEE Trans. Fuzzy Syst. 4(4): 502-505 (1996)
Coauthor Index
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