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Sailesh K. Rao
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1990 – 1999
- 1997
- [j7]Giovanni Cherubini, Sedat Ölçer, Gottfried Ungerboeck, John Creigh, Sailesh K. Rao:
100BASE-T2: a new standard for 100 Mb/s Ethernet transmission over voice-grade cables. IEEE Commun. Mag. 35(11): 115-122 (1997) - [c6]Giovanni Cherubini, John Creigh, Sedat Ölçer, Sailesh K. Rao, Gottfried Ungerboeck:
100BASE-T2: 100 Mbit/s Ethernet over Two Pairs of Category-3 Cabling. ICC (2) 1997: 1014-1018 - 1995
- [j6]Sailesh K. Rao, Mehdi Hatamian:
The ATM physical layer. Comput. Commun. Rev. 25(2): 73-81 (1995) - 1994
- [c5]Alex G. Dickinson, Chris J. Nicol, Sailesh K. Rao, M. Hatamian:
Application Specific Memories for ATM Packet Switching. ISCAS 1994: 169-172 - 1992
- [j5]Sailesh K. Rao, P. Sadayappan, Frank K. Hwang, Peter W. Shor:
The Rectilinear Steiner Arborescence Problem. Algorithmica 7(2&3): 277-288 (1992) - 1990
- [j4]Juan-Manuel Jover, Thomas Kailath, Hanoch Lev-Ari, Sailesh K. Rao:
On the Analysis of Synchronous Computing Systems. SIAM J. Comput. 19(4): 627-643 (1990) - [c4]Sailesh K. Rao, Mehdi Hatamian, Bryan D. Ackland:
A design environment for high performance VLSI signal processing. ICCD 1990: 147-152
1980 – 1989
- 1989
- [c3]Sailesh K. Rao:
The matrix transform chip. ICCD 1989: 86-89 - [c2]Ponnuswamy Sadayappan, Sailesh K. Rao:
Communication reduction for distributed sparse matrix factorization on a processor mesh. SC 1989: 371-379 - 1988
- [j3]Sailesh K. Rao, Thomas Kailath:
Regular iterative algorithms and their implementation on processor arrays. Proc. IEEE 76(3): 259-269 (1988) - 1987
- [j2]Sailesh K. Rao, Chi-Tsong Chen:
Design of minimal-degree compensators with assignable poles or structure. Autom. 23(2): 241-245 (1987) - [j1]Hosagrahar Visvesvaraya Jagadish, Sailesh K. Rao, Thomas Kailath:
Array architectures for iterative algorithms. Proc. IEEE 75(9): 1304-1321 (1987) - 1984
- [c1]Sailesh K. Rao, Thomas Kailath:
Pipelined orthogonal digital lattice filters. ICASSP 1984: 464-467
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