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ORCIDRazali Jidin
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2010 – 2019
- 2019
[c9]Razali Jidin, M. Reyasudin Basir Khan, Norziana Jamil, Ibrahim Al-Bahadly:
Prospective Control Systems and Cyber-Securities for Electrical Secondary Substations. ICCSCE 2019: 99-103- 2016
- [j2]Haider Ismael Shahadi, Razali Jidin, Wong Hung Way:
Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA. Comput. Electr. Eng. 49: 95-116 (2016) - 2015
- [c8]Razali Jidin, Abdul Bahari Othman:
Cascade hydroelectric scheme: River flow estimation for reservoir regulation improvement and flood-risk mitigation. ICCSCE 2015: 315-319 - 2014
- [c7]Saad Al-Azawi
, Yasir Amer Abbas, Razali Jidin:
Low complexity multidimensional CDF 5/3 DWT architecture. CSNDSP 2014: 804-808 - 2013
- [c6]Liang Wei, S. C. Mukhopadhyay, Razali Jidin, Chia-Pang Chen:
Multi-source information fusion for drowsy driving detection based on wireless sensor networks. ICST 2013: 850-857 - 2011
- [c5]Haider Ismael Shahadi, Razali Jidin:
High capacity and inaudibility audio steganography scheme. IAS 2011: 104-109 - 2010
- [c4]Syed Zahidul Islam, Mohd. Alauddin Mohd. Ali, Razali Jidin, Syed Zahurul Islam:
Embedded system based driver drowsiness detection system. ICDIP 2010: 754614 - [c3]Syed Zahurul, Syed Zahidul, Razali Jidin:
An Adept Edge Detection Algorithm for Human Knee Osteoarthritis Images. ICSAP 2010: 375-379
2000 – 2009
- 2005
- [c2]Razali Jidin, David Andrews, Wesley Peck, Dan Chirpich, Kevin Stout, John M. Gauch:
Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms. IPDPS 2005 - 2004
- [j1]David Andrews, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge L. Ortiz, Ed Komp, Peter J. Ashenden:
Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link. IEEE Micro 24(4): 42-53 (2004) - [c1]Razali Jidin, David L. Andrews, Douglas Niehaus:
Implementing Multi Threaded System Support for Hybrid FPGA/CPU Computational Components. ERSA 2004: 116-122
Coauthor Index
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