default search action
Magnus Själander
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j19]Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Magnus Själander, Klaus D. McDonald-Maier:
ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2944-2957 (2024) - [c49]Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier:
MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. DAC 2024: 92:1-92:6 - [c48]Sukarn Agarwal, Shounak Chakraborty, Magnus Själander:
TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. IPDPS 2024: 852-864 - [i9]Jacob O. Tørring, Carl Hvarfner, Luigi Nardi, Magnus Själander:
CATBench: A Compiler Autotuning Benchmarking Suite for Black-box Optimization. CoRR abs/2406.17811 (2024) - [i8]David Metz, Nico Reissmann, Magnus Själander:
R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges. CoRR abs/2408.08712 (2024) - 2023
- [j18]Christos Sakalis, Stefanos Kaxiras, Magnus Själander:
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks. ACM Trans. Archit. Code Optim. 20(1): 9:1-9:24 (2023) - [j17]David Metz, Vineet Kumar, Magnus Själander:
BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers. ACM Trans. Embed. Comput. Syst. 22(5): 79:1-79:22 (2023) - [j16]Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier:
DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Trans. Parallel Distributed Syst. 34(2): 718-733 (2023) - [c47]Sukarn Agarwal, Shounak Chakraborty, Magnus Själander:
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). DAC 2023: 1-6 - [c46]Amund Bergland Kvalsvik, Pavlos Aimoniotis, Stefanos Kaxiras, Magnus Själander:
Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes. ISCA 2023: 53:1-53:13 - [c45]Pavlos Aimoniotis, Amund Bergland Kvalsvik, Xiaoyue Chen, Magnus Själander, Stefanos Kaxiras:
ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage. MICRO 2023: 828-842 - 2022
- [c44]Shounak Chakraborty, Vassos Soteriou, Magnus Själander:
STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. CF 2022: 21-29 - [c43]Pavlos Aimoniotis, Amund Bergland Kvalsvik, Magnus Själander, Stefanos Kaxiras:
Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes. SEED 2022: 49-60 - 2021
- [j15]Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras:
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions. IEEE Comput. Archit. Lett. 20(2): 162-165 (2021) - [j14]Shounak Chakraborty, Magnus Själander:
WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. ACM Trans. Archit. Code Optim. 18(4): 55:1-55:25 (2021) - [j13]Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier:
Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. ACM Trans. Embed. Comput. Syst. 20(5s): 62:1-61:25 (2021) - [c42]Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu:
Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. SEED 2021: 89-100 - [c41]Christos Sakalis, Magnus Själander, Stefanos Kaxiras:
Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference. SEED 2021: 101-107 - [i7]Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu:
On Value Recomputation to Accelerate Invisible Speculation. CoRR abs/2102.10932 (2021) - [i6]Christos Sakalis, Stefanos Kaxiras, Magnus Själander:
Selectively Delaying Instructions to Prevent Microarchitectural Replay Attacks. CoRR abs/2103.10692 (2021) - [i5]Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras:
"It's a Trap!"-How Speculation Invariance Can Be Abused with Forward Speculative Interference. CoRR abs/2109.10774 (2021) - 2020
- [j12]Christos Sakalis, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander:
Evaluating the Potential Applications of Quaternary Logic for Approximate Computing. ACM J. Emerg. Technol. Comput. Syst. 16(1): 5:1-5:25 (2020) - [j11]Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander:
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. IEEE Trans. Computers 69(11): 1584-1595 (2020) - [c40]Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean:
Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. PACT 2020: 241-254 - [c39]Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier:
RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress. CODES+ISSS 2020: 8-10 - [c38]Rajiv Nishtala, Vinicius Petrucci, Paul M. Carpenter, Magnus Själander:
Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services. HPCA 2020: 167-179
2010 – 2019
- 2019
- [j10]Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander:
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. 12(3): 15:1-15:24 (2019) - [c37]Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander:
Ghost loads: what is the cost of invisible speculation? CF 2019: 153-163 - [c36]Lahiru Rasnayake, Magnus Själander:
Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing. FPT 2019: 415-418 - [c35]Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander:
Efficient invisible speculative execution through selective delay and value prediction. ISCA 2019: 723-735 - [i4]Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander:
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. CoRR abs/1901.00370 (2019) - [i3]Nico Reissmann, Jan Christian Meyer, Helge Bahmann, Magnus Själander:
RVSDG: An Intermediate Representation for Optimizing Compilers. CoRR abs/1912.05036 (2019) - [i2]Magnus Själander, Magnus Jahre, Gunnar Tufte, Nico Reissmann:
EPIC: An Energy-Efficient, High-Performance GPGPU Computing Research Infrastructure. CoRR abs/1912.05848 (2019) - 2018
- [j9]Kim-Anh Tran, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Vasileios Spiliopoulos, Stefanos Kaxiras, Alexandra Jimborean:
Static Instruction Scheduling for High Performance on Limited Hardware. IEEE Trans. Computers 67(4): 513-527 (2018) - [c34]Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander:
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. FPL 2018: 307-314 - [c33]Kim-Anh Tran, Alexandra Jimborean, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras:
SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores. PLDI 2018: 328-343 - [i1]Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander:
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. CoRR abs/1806.08862 (2018) - 2017
- [j8]Trevor E. Carlson, Kim-Anh Tran, Alexandra Jimborean, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras:
Transcending Hardware Limits with Software Out-of-Order Processing. IEEE Comput. Archit. Lett. 16(2): 162-165 (2017) - [c32]Kim-Anh Tran, Trevor E. Carlson, Konstantinos Koukos, Magnus Själander, Vasileios Spiliopoulos, Stefanos Kaxiras, Alexandra Jimborean:
Clairvoyance: look-ahead compile-time scheduling. CGO 2017: 171-184 - 2016
- [c31]Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee:
Redesigning a tagless access buffer to require minimal ISA changes. CASES 2016: 19:1-19:10 - [c30]Magnus Själander, Gustaf Borgström, Mykhailo V. Klymenko, Françoise Remacle, Stefanos Kaxiras:
Techniques for modulating error resilience in emerging multi-value technologies. Conf. Computing Frontiers 2016: 55-63 - [c29]Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Practical way halting by speculatively accessing halt tags. DATE 2016: 1375-1380 - [c28]Thiemo Voigt, Magnus Själander, Frederik Hermans:
Poster: Approximation: A New Paradigm also for Wireless Sensing. EWSN 2016: 221-222 - 2015
- [c27]B. Davis, Ryan Baird, Peter Gavin, Magnus Själander, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson:
Scheduling instruction effects for a statically pipelined processor. CASES 2015: 167-176 - [c26]Ryan Baird, Peter Gavin, Magnus Själander, David B. Whalley, Gang-Ryung Uh:
Optimizing Transfers of Control in the Static Pipeline Architecture. LCTES 2015: 1:1-1:10 - [c25]Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Improving Data Access Efficiency by Using Context-Aware Loads and Stores. LCTES 2015: 3:1-3:10 - 2014
- [b1]Magnus Själander, Margaret Martonosi, Stefanos Kaxiras:
Power-Efficient Computer Architectures: Recent Advances. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2014, ISBN 978-3-031-00617-3 - [c24]Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3). DATE 2014: 1-4 - [c23]Magnus Själander, Nina Shariati Nilsson, Stefanos Kaxiras:
A tunable cache for approximate computing. NANOARCH 2014: 88-89 - 2013
- [j7]Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Designing a practical data filter cache to improve both energy efficiency and performance. ACM Trans. Archit. Code Optim. 10(4): 54:1-54:25 (2013) - [j6]Peter Gavin, David B. Whalley, Magnus Själander:
Reducing instruction fetch energy in multi-issue processors. ACM Trans. Archit. Code Optim. 10(4): 64:1-64:24 (2013) - [c22]Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström:
Improving data access efficiency by using a tagless access buffer (TAB). CGO 2013: 28:1-28:11 - [c21]Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Speculative tag access for reduced energy dissipation in set-associative L1 data caches. ICCD 2013: 302-308 - [c20]Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David B. Whalley, Magnus Själander, Gary S. Tyson:
Improving processor efficiency by statically pipelining instructions. LCTES 2013: 33-44 - [c19]Magnus Själander, Per Larsson-Edefors:
FlexCore: Implementing an exposed datapath processor. ICSAMOS 2013: 306-313 - 2012
- [j5]Bhavishya Goel, Sally A. McKee, Magnus Själander:
Techniques to Measure, Model, and Manage Power. Adv. Comput. 87: 7-54 (2012) - [c18]Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors:
Viterbi Accelerator for Embedded Processor Datapaths. ASAP 2012: 133-140 - [c17]Magnus Själander, Sally A. McKee, Peter Brauer, David Engdal, András Vajda:
An LTE Uplink Receiver PHY benchmark and subframe-based power management. ISPASS 2012: 25-34 - [c16]Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors:
Configurable RTL model for level-1 caches. NORCHIP 2012: 1-4 - 2011
- [c15]Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors:
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. IPDPS Workshops 2011: 322-325 - [c14]Magnus Själander, Sally A. McKee, Bhavishya Goel, Peter Brauer, David Engdal, András Vajda:
Power-Aware Resource Scheduling in Base Stations. MASCOTS 2011: 462-465 - 2010
- [j4]Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3073-3081 (2010) - [c13]Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors:
Design space exploration for an embedded processor with flexible datapath interconnect. ASAP 2010: 55-62
2000 – 2009
- 2009
- [j3]Magnus Själander, Per Larsson-Edefors:
Multiplication Acceleration Through Twin Precision. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1233-1246 (2009) - [j2]Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström:
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. J. Signal Process. Syst. 57(1): 5-19 (2009) - [c12]Martin Thuresson, Magnus Själander, Per Stenström:
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. HiPEAC 2009: 95-109 - [c11]Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander, Henrik Eriksson, Per Larsson-Edefors:
Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. ICECS 2009: 77-80 - [c10]Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. IPDPS 2009: 1-7 - [c9]Thomas Schilling, Magnus Själander, Per Larsson-Edefors:
Scheduling for an Embedded Architecture with a Flexible Datapath. ISVLSI 2009: 151-156 - [c8]Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. SoCC 2009: 119-122 - 2008
- [j1]Md. Mafijul Islam, Magnus Själander, Per Stenström:
Early detection and bypassing of trivial operations to improve energy efficiency of processors. Microprocess. Microsystems 32(4): 183-196 (2008) - [c7]Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton:
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. DSD 2008: 149-157 - [c6]Magnus Själander, Per Larsson-Edefors:
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree. ICECS 2008: 33-36 - 2007
- [c5]Magnus Själander, Per Larsson-Edefors, Magnus Björk:
A Flexible Datapath Interconnect for Embedded Applications. ISVLSI 2007: 15-20 - [c4]Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström:
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS 2007: 18-25 - 2006
- [c3]Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, Daniel Johansson, Martin Scholin:
Multiplier reduction tree with logarithmic logic depth and regular connectivity. ISCAS 2006 - 2005
- [c2]Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson:
A low-leakage twin-precision multiplier using reconfigurable power gating. ISCAS (2) 2005: 1654-1657 - 2004
- [c1]Magnus Själander, Henrik Eriksson, Per Larsson-Edefors:
An Efficient Twin-Precision Multiplier. ICCD 2004: 30-33
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from , , and to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-02 22:35 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint