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ORCIDHaoran Li 0016
Person information
Other persons with the same name
- Haoran Li — disambiguation page
- Haoran Li 0001
![[0000-0002-2368-7541]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-2368-7541")
— JD AI Research (and 2 more) - Haoran Li 0002 — Alibaba DAMO Academy Computing Technology Laboratory, Hangzhou, China (and 1 more)
- Haoran Li 0003 — Peking University, School of EECS, Beijing, China
- Haoran Li 0004 — Anhui University, School of Electrical Engineering and Automation, Hefei, China (and 1 more)
- Haoran Li 0005 — Arizona State University, Tempe, AZ, USA
- Haoran Li 0006 — Shenzhen University, China (and 1 more)
- Haoran Li 0007 — Meta AI (and 1 more)
- Haoran Li 0008 — Wuhan University, Wuhan, Hubei, China
- Haoran Li 0009 — Sun Yat-sen University, Department of School of Electronics and Communication Engineering, Shenzhen, China (and 1 more)
- Haoran Li 0010 — Chinese Academy of Sciences, State Key Laboratory of Management and Control for Complex Systems, Beijing, China (and 2 more)
- Haoran Li 0011 — Carnegie Mellon University, Machine Learning Department, Pittsburgh, PA, USA (and 1 more)
- Haoran Li 0012
- Haoran Li 0013
- Haoran Li 0014
- Haoran Li 0015
- Haoran Li 0017
- Haoran Li 0018
- Haoran Li 0019
- Haoran Li 0020
- Haoran Li 0021
- Haoran Li 0022
- Haoran Li 0023 — Northeastern University, China (and 1 more)
- Haoran Li 0024
- Haoran Li 0025
- Haoran Li 0026
- Haoran Li 0027 — University of the Chinese Academy of Sciences, China
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2020 – today
- 2025
[j3]Tailong Xu, Haoran Li, Xi Meng, Xiangxun Zhan, Yatao Peng, Jun Yin, Shiheng Yang, Chao Fan, Zhixiang Huang, Rui Paulo Martins, Pui-In Mak:
Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. IEEE Trans. Circuits Syst. II Express Briefs 72(3): 439-443 (2025)- [c3]Haoran Li, Jinge Li, Xueying Jiang, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak:
19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms Jitter, -249.7dB FoM, and 1.98µS Locking Time Using Polarity-Reversible SSPD. ISSCC 2025: 1-3 - 2024
- [j2]Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak:
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment. IEEE J. Solid State Circuits 59(12): 3952-3965 (2024) - [c2]Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak:
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. ISSCC 2024: 204-206 - 2023
- [j1]Xi Meng, Haoran Li, Peng Chen, Jun Yin, Pui-In Mak, Rui Paulo Martins:
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5110-5123 (2023) - 2021
- [c1]Xi Meng, Junqi Guo, Haoran Li, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS. A-SSCC 2021: 1-3
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