A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS.

Tue, 01 Jul 2025 01:00:00 +0200

Hua Xu , Mingche Lai , Xuqiang Zheng , Zedong Wang , Jiang Xu, Sai Li , Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo , Xinhua Wang , Zhi Jin , Xinyu Liu :
A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. IEEE J. Solid State Circuits 60(7): 2305-2318 (2025)