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ORCIDR. V. K. Pillai
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2000 – 2009
- 2001
[j1]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah:
A Low Power Approach to Floating Point Adder Design for DSP Applications. J. VLSI Signal Process. 27(3): 195-213 (2001)- [c7]R. V. K. Pillai, S. Y. A. Shah, A. J. Al-Khalili, Dhamin Al-Khalili:
Low power floating point MAFs-a comparative study. ISSPA 2001: 284-287
1990 – 1999
- 1999
- [c6]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
An IEEE Compliant Floating Point MAF. VLSI 1999: 149-160 - [c5]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Power implications of precision limited arithmetic in floating point FIR filters. ISCAS (1) 1999: 165-168 - 1998
- [c4]R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili:
A Low Power Floating Point Accumulator. VLSI Design 1998: 330- - 1997
- [c3]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
A Low Power Approach to Floating Point Adder Design. ICCD 1997: 178-185 - [c2]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. ISLPED 1997: 235-238 - 1996
- [c1]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Energy delay analysis of partial product reduction methods for parallel multiplier implementation. ISLPED 1996: 201-204
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