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Janampalli Pavanija

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2024
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Mandar Datar, Dhruva S. Hegde, Vendra Durga Prasad, Manish Prajapati, Neralla Manikanta, Devansh Gupta, Janampalli Pavanija, Pratyush Pare, Akash, Shivam Gupta, Sachin B. Patkar:
Python-based DSL for generating Verilog model of Synchronous Digital Circuits. CoRR abs/2406.09208 (2024)

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