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Chau-Shen Chen

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2000 – 2009

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2001
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Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 383-389 (2001)

1990 – 1999

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1998
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Chau-Shen Chen, TingTing Hwang:
Layout Driven Selection and Chaining of Partial Scan Flip-Flops. J. Electron. Test. 13(1): 19-27 (1998)
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Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning. ICCAD 1998: 408-411
1997
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Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661
1996
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Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang:
Layout Driven Selecting and Chaining of Partial Scan. DAC 1996: 262-267
1995
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Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1076-1084 (1995)
1993
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Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127

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