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Journal Articles
- 2025
[j1]Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng, Jianfei Jiang, Zhigang Mao:
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. IEEE Trans. Very Large Scale Integr. Syst. 33(6): 1502-1515 (2025)
Conference and Workshop Papers
- 2024
- [c3]Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang:
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. ISCAS 2024: 1-5 - 2023
- [c2]Xiaoyan Li, Zizheng Dong, Shuaipeng Li, Sai Gao, Jianfei Jiang, Guanghui He, Zhigang Mao:
MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5. ASICON 2023: 1-4 - [c1]Han Liu, Nan Qi, Donglai Lu, Zizheng Dong, Zhihan Zhang, Jian He, Guike Li, Leliang Li, Ye Liu, Ziyue Dang, Daigao Chen, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Liyuan Liu:
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. A-SSCC 2023: 1-3
Coauthor Index
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