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ORCIDEmre Ozer 0001
Person information
- affiliation: Pragmatic Semiconductor, Cambridge, UK
- affiliation (former): Arm Ltd., Cambridge, UK
- affiliation (former): Trinity College Dublin, Ireland
- affiliation (former, PhD 2001): North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, NC, USA
Other persons with the same name
- Emre Özer (aka: Emre Ozer) — disambiguation page
- Emre Özer 0002
![[0000-0002-0951-2892]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-0951-2892")
— Istanbul University-Cerrahpaşa, Department of Electrical and Energy, Turkey
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2020 – today
- 2023
[i1]Konstantinos Iordanou, Timothy Atkinson, Emre Ozer, Jedrzej Kufel, John Biggs, Gavin Brown, Mikel Luján:
Tiny Classifier Circuits: Evolving Accelerators for Tabular Data. CoRR abs/2303.00031 (2023)
2010 – 2019
- 2018
- [j8]Xabier Iturbe, Balaji Venu, Juergen Jagst, Emre Ozer, Peter Harrod, Chris Turner, John Penton:
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture. IEEE Des. Test 35(3): 7-14 (2018) - [j7]Xabier Iturbe, Balaji Venu, Emre Ozer, Jean-Luc Poupat, Gregoire Gimenez, Hans-Ulrich Zurek:
The Arm Triple Core Lock-Step (TCLS) Processor. ACM Trans. Comput. Syst. 36(3): 7:1-7:30 (2018) - [c32]Emre Ozer, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton:
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. MICRO 2018: 737-748 - 2017
- [c31]Xabier Iturbe, Balaji Venu, John Penton, Emre Ozer:
A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress. CASES 2017: 6:1-6:2 - 2016
- [j6]Marios Kleanthous, Yiannakis Sazeides, Emre Özer, Chrysostomos Nicopoulos, Panagiota Nikolaou, Zacharias Hadjilambrou:
Toward Multi-Layer Holistic Evaluation of System Designs. IEEE Comput. Archit. Lett. 15(1): 58-61 (2016) - [j5]Ravi R. Iyer, Emre Ozer:
Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT. IEEE Micro 36(6): 45-49 (2016) - [c30]Xabier Iturbe, Balaji Venu, Emre Ozer:
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU. DFT 2016: 91-96 - [c29]Xabier Iturbe, Balaji Venu, Emre Ozer, Shidhartha Das:
A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications. DSN Workshops 2016: 246-249 - [c28]Yordan P. Raykov, Emre Ozer, Ganesh Dasika, Alexis Boukouvalas, Max A. Little:
Predicting room occupancy with a single passive infrared (PIR) sensor through behavior extraction. UbiComp 2016: 1016-1027 - 2015
- [c27]Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin P. Hand, Robert Carlson, Emre Ozer:
Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation. AHS 2015: 1-8 - [c26]Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin P. Hand, Robert Carlson, Emre Ozer:
A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing. FCCM 2015: 231 - [c25]Xabier Iturbe, Didier Keymeulen, Emre Ozer, Patrick Yiu, Daniel Berisford, Kevin P. Hand, Robert Carlson:
Designing a SoC to control the next-generation space exploration flight science instruments. SoCC 2015: 13-18 - [c24]Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Daniel Berisford, Robert Carlson, Kevin P. Hand, Emre Ozer:
On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration. VLSI-SoC (Selected Papers) 2015: 1-22 - [c23]Xabier Iturbe, Didier Keymeulen, Emre Ozer, Patrick Yiu, Daniel Berisford, Kevin P. Hand, Robert Carlson:
An integrated SoC for science data processing in next-generation space flight instruments avionics. VLSI-SoC 2015: 134-141 - 2013
- [c22]Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer, Sachin Idgunji:
Memory array protection: check on read or check on write? DATE 2013: 214-219 - [c21]Damien Hardy, Marios Kleanthous, Isidoros Sideris, Ali G. Saidi, Emre Ozer, Yiannakis Sazeides:
An analytical framework for estimating TCO and exploring data center design space. ISPASS 2013: 54-63 - [c20]Yiannakis Sazeides, Emre Özer, Danny Kershaw, Panagiota Nikolaou, Marios Kleanthous, Jaume Abella:
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes. MICRO 2013: 160-171 - 2012
- [c19]Dragomir Milojevic, Sachin Idgunji, Djordje Jevdjic, Emre Ozer, Pejman Lotfi-Kamran, Andreas Panteli, Andreas Prodromou, Chrysostomos Nicopoulos, Damien Hardy, Babak Falsafi, Yiannakis Sazeides:
Thermal characterization of cloud workloads on a power-efficient server-on-chip. ICCD 2012: 175-182 - [c18]Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, Stavros Volos, Yusuf Onur Koçberber, Javier Picorel, Almutaz Adileh, Djordje Jevdjic, Sachin Idgunji, Emre Ozer, Babak Falsafi:
Scale-out processors. ISCA 2012: 500-511 - 2011
- [c17]Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Emre Özer:
Radiation hardening by design: A novel gate level approach. AHS 2011: 74-79 - [c16]Bushra Ahsan, Lorena Ndreu, Isidoros Sideris, Yiannakis Sazeides, Sachin Idgunji, Emre Özer:
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays. ISLPED 2011: 181-186
2000 – 2009
- 2009
- [c15]Mrinmoy Ghosh, Emre Özer, Simon Ford, Stuart Biles, Hsien-Hsin S. Lee:
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches. ISLPED 2009: 165-170 - 2008
- [j4]Emre Özer, Andy Nisbet, David Gregg:
A stochastic bitwidth estimation technique for compact and low-power custom processors. ACM Trans. Embed. Comput. Syst. 7(3): 34:1-34:30 (2008) - [c14]Emre Özer, Ronald G. Dreslinski, Trevor N. Mudge, Stuart Biles, Krisztián Flautner:
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. SAMOS 2008: 12-22 - 2007
- [c13]Emre Özer, Stuart Biles:
Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor. Asia-Pacific Computer Systems Architecture Conference 2007: 376-386 - [c12]Emre Özer, Alastair Reid, Stuart Biles:
Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor. SBAC-PAD 2007: 37-44 - 2006
- [j3]Yunhe Shi, Emre Özer, David Gregg:
Analyzing Effects of Trace Cache Configurations on the Prediction of Indirect Branches. J. Instr. Level Parallelism 8 (2006) - [c11]Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee:
Efficient System-on-Chip Energy Management with a Segmented Bloom Filter. ARCS 2006: 283-297 - [c10]Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee:
Reducing energy of virtual cache synonym lookup using bloom filters. CASES 2006: 179-189 - [c9]Yunhe Shi, Emre Özer, David Gregg:
Low-Cost Microarchitectural Techniques for Enhancing the Prediction of Return Addresses on High-Performance Trace Cache Processors. ISCIS 2006: 248-257 - 2005
- [j2]Emre Özer, Andy Nisbet, David Gregg, Owen Callanan:
Estimating data bus size for custom processors in embedded systems. Des. Autom. Embed. Syst. 10(1): 5-26 (2005) - [j1]Emre Özer, Thomas M. Conte:
High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. IEEE Trans. Parallel Distributed Syst. 16(12): 1132-1142 (2005) - [c8]Owen Callanan, Andy Nisbet, Emre Özer, James Sexton, David Gregg:
FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic. IPDPS 2005 - [c7]Emre Özer, Resit Sendag, David Gregg:
Multiple-Valued Caches for Power-Efficient Embedded Systems. ISMVL 2005: 126-131 - 2004
- [c6]Emre Özer, Andy Nisbet, David Gregg:
Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors. CC 2004: 250-264 - [c5]Emre Özer, Andy Nisbet, David Gregg:
Automatic Customization of Embedded Applications for Enhanced Performance and Reduced Power Using Optimizing Compiler Techniques. Euro-Par 2004: 318-327 - [c4]Emre Özer, Andy Nisbet, David Gregg:
Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs. FCCM 2004: 273-274 - 2001
- [c3]Emre Özer, Thomas M. Conte, Saurabh Sharma:
Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. HiPC 2001: 192-203
1990 – 1999
- 1998
- [c2]Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte:
A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT 1998: 136-141 - [c1]Emre Özer, Sanjeev Banerjia, Thomas M. Conte:
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. MICRO 1998: 308-315
Coauthor Index
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