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Kumiko Nomura
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2020 – today
- 2024
- [i1]Kumiko Nomura, Yoshifumi Nishi:
Synchronized Stepwise Control of Firing and Learning Thresholds in a Spiking Randomly Connected Neural Network toward Hardware Implementation. CoRR abs/2404.17241 (2024) - 2020
- [c17]Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi:
Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c16]Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi:
Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning. ISCAS 2019: 1-5 - 2018
- [c15]Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi:
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. ISCAS 2018: 1-5 - 2017
- [c14]Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe:
Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT 2017: 1-2 - 2014
- [c13]Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe:
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". ASP-DAC 2014: 6-11 - [c12]Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe:
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC 2014: 316-319 - 2013
- [c11]Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE 2013: 1813-1818 - 2012
- [c10]Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita:
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops 2012: 213-220 - 2010
- [c9]Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima:
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. ISCAS 2010: 2876-2879
2000 – 2009
- 2009
- [j4]Satoshi Tayu, Kumiko Nomura, Shuichi Ueno:
On the two-dimensional orthogonal drawing of series-parallel graphs. Discret. Appl. Math. 157(8): 1885-1895 (2009) - [c8]Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto:
Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS 2009: 73-76 - 2008
- [c7]Satoshi Tayu, Kumiko Nomura, Shuichi Ueno:
On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract). ISCAS 2008: 212-215 - 2007
- [j3]Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee:
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2472-2479 (2007) - 2006
- [c6]Satoshi Tayu, Kumiko Nomura, Shuichi Ueno:
On the two-dimensional orthogonal drawing of series-parallel graphs. ISCAS 2006 - [c5]Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee:
3D on-chip networking technology based on post-silicon devices for future networks-on-chip. Nano-Net 2006: 1-5 - [c4]Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon:
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net 2006: 1-5 - 2005
- [j2]Kumiko Nomura, Satoshi Tayu, Shuichi Ueno:
On the Orthogonal Drawing of Outerplanar Graphs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1583-1588 (2005) - 2004
- [j1]Toshinori Yamada, Kumiko Nomura, Shuichi Ueno:
Sparse networks tolerating random faults. Discret. Appl. Math. 137(2): 223-235 (2004) - [c3]Kumiko Nomura, Satoshi Tayu, Shuichi Ueno:
On the Orthogonal Drawing of Outerplanar Graphs. COCOON 2004: 300-308 - 2003
- [c2]Toshinori Yamada, Kumiko Nomura, Shuichi Ueno:
Optimal adaptive parallel diagnosis for arrays. ISCAS (3) 2003: 854-857 - 2001
- [c1]Kumiko Nomura, Toshinori Yamada, Shuichi Ueno:
On Adaptive Fault Diagnosis for Multiprocessor Systems. ISAAC 2001: 86-98
Coauthor Index
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