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ORCIDHongzhuo Liu
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2020 – today
- 2024
[j2]Hongzhuo Liu
, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Zhihua Wang, Baoyong Chi:
A Multireference PLL: Theory and Implementation. IEEE J. Solid State Circuits 59(7): 1981-1994 (2024)- [j1]Qixiu Wu, Wei Deng, Yaqian Sun, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi:
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique. IEEE J. Solid State Circuits 59(8): 2441-2454 (2024) - [c7]Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi:
An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. CICC 2024: 1-2 - 2023
- [c6]Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng, Zhihua Wang, Baoyong Chi:
IEEE ASSCC 2023/ Session 10/ Paper 10.5. A-SSCC 2023: 1-3 - [c5]Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi:
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. CICC 2023: 1-2 - [c4]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi:
A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. ESSCIRC 2023: 261-264 - [c3]Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi:
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. ISSCC 2023: 146-147 - [c2]Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi:
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c1]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi:
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv. ESSCIRC 2022: 233-236
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