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ORCIDBernard Goossens
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2020 – today
- 2021
[c14]Bernard Goossens, Kenelm Louetsi, David Parello:
Deterministic OpenMP and the LBP Parallelizing Manycore Processor. PaCT 2021: 26-40
2010 – 2019
- 2017
- [j8]Bernard Goossens, David Parello, Katarzyna Porada, Djallal Rahmoune:
Computing on many cores. Concurr. Comput. Pract. Exp. 29(15) (2017) - 2016
- [c13]Bernard Goossens, David Parello, Katarzyna Porada, Djallal Rahmoune:
Parallel Locality and Parallelization Quality. PMAM@PPoPP 2016: 59-68 - 2015
- [c12]Bernard Goossens, David Parello, Katarzyna Porada, Djallal Rahmoune:
Toward a Core Design to Distribute an Execution on a Manycore Processor. PaCT 2015: 390-404 - 2013
- [j7]Bernard Goossens, Ali El Moussaoui, Ke Chen, David Parello:
De quoi est faite une trace d'exécution ? Tech. Sci. Informatiques 32(2): 229-252 (2013) - [c11]Bernard Goossens, David Parello:
Limits of Instruction-Level Parallelism Capture. ICCS 2013: 1664-1673 - 2011
- [j6]Mourad Bouache, David Parello, Bernard Goossens:
Accélération de la simulation modulaire. Tech. Sci. Informatiques 30(9): 1115-1134 (2011) - 2010
- [c10]Bernard Goossens, Philippe Langlois, David Parello, Eric Petit:
PerPI: A Tool to Measure Instruction Level Parallelism. PARA (1) 2010: 270-281
2000 – 2009
- 2009
- [c9]Benaoumeur Senouci, Ali El Moussaoui
, Bernard Goossens:
Software Platform based Embedded Multiprocessor SoC Prototyping. CIIA 2009 - [c8]Benaoumeur Senouci, Mourad Bouache, Bernard Goossens:
Heterogeneous Multi-processor SoC Design: Hardware Bridging and Exploration Methodology. ESA 2009: 204-210 - 2006
- [j5]Bernard Goossens, David Defour:
Ordonnancement distribué d'instructions. Tech. Sci. Informatiques 25(7): 827-844 (2006) - 2005
- [j4]Bernard Goossens, David Defour:
The instruction register file micro-architecture. Future Gener. Comput. Syst. 21(4): 767-773 (2005) - 2003
- [c7]Bernard Goossens:
The Instruction Register File. PaCT 2003: 467-481 - 2002
- [j3]Bernard Goossens:
Typing the ISA to cluster the processor. Future Gener. Comput. Syst. 18(6): 789-796 (2002) - 2001
- [j2]Bernard Goossens:
Handling 16 instructions per cycle in a superscalar processor. Future Gener. Comput. Syst. 17(6): 699-709 (2001) - [c6]Bernard Goossens:
Typing the ISA to Cluster the Processor. PaCT 2001: 232-242
1990 – 1999
- 1999
- [c5]Bernard Goossens, Hassane Essafi, Marc Pic:
Hardware and Software Optimizations for Multimedia Databases. PaCT 1999: 365-370 - 1997
- [c4]Bernard Goossens:
A Multithreaded Vector Co-processor. PaCT 1997: 311-321 - 1996
- [j1]Bernard Goossens:
Les architectures risc et polo: un processeur oriente objet. Bull. dInformatique Approfondie et Appl. 43: 7-36 (1996) - [c3]Bernard Goossens, Duc Thang Vu:
On-Chip Multiprocessing. Euro-Par, Vol. II 1996: 789-796 - [c2]Bernard Goossens, Duc Thang Vu:
Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors. ISPAN 1996: 36-42 - 1995
- [c1]Bernard Goossens, Duc Thang Vu:
Further Pipelining and Multithreading to Improve RISC Processor Speed. A Proposed Architecture and Simulation Results. PaCT 1995: 326-340
Coauthor Index
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