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Manabu Ichinose

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1990 – 1999

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1997
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  - https://dblp.org/rec/journals/jssc/SunagaHNII97
Toshio Sunaga, Koji Hosokawa, Yutaka Nakamura, Manabu Ichinose, Yasuyuki Igarashi:
An eight-bit prefetch circuit for high-bandwidth DRAM's. IEEE J. Solid State Circuits 32(1): 105-110 (1997)

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