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Gajanan Jedhe
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2020 – today
- 2024
- [c4]Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, Ming-Hung Lin, Pei-Kuei Tsung, En-Jui Chang, Jenwei Liang, Shu-Hsin Chang, Chung-Lun Huang, You-Yu Nian, Zhe Wan, Sushil Kumar, Cheng-Xin Xue, Gajanan Jedhe, Hidehiro Fujiwara, Haruki Mori, Chih-Wei Chen, Po-Hua Huang, Chih-Feng Juan, Chung-Yi Chen, Tsung-Yao Lin, Ch Wang, Chih-Cheng Chen, Kevin Jou:
20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices. ISSCC 2024: 360-362 - 2023
- [c3]En-Jui Chang, Cheng-Xin Xue, Chetan Deshpande, Gajanan Jedhe, Jenwei Liang, Chih-Chung Cheng, Hung-Wei Lin, Chia-Da Lee, Sushil Kumar, Kim Soon Jway, Zijie Guo, Ritesh Garg, Allen-Cl Lu, Chien-Hung Lin, Meng-Han Hsieh, Tsung-Yao Lin, Chih-Cheng Chen:
A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision. VLSI Technology and Circuits 2023: 1-2 - [c2]Gajanan Jedhe, Chetan Deshpande, Sushil Kumar, Cheng-Xin Xue, Zijie Guo, Ritesh Garg, Kim Soon Jway, En-Jui Chang, Jenwei Liang, Zhe Wan, Zhenhao Pan:
A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications. VLSI Technology and Circuits 2023: 1-2 - 2021
- [c1]Chetan Deshpande, Ritesh Garg, Gajanan Jedhe, Gaurang Narvekar, Sushil Kumar:
A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs. VLSI Circuits 2021: 1-2
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last updated on 2024-04-24 22:59 CEST by the dblp team
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