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2020 – today
- 2024
[j1]Ashwin Sanjay Lele
, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits 59(1): 52-64 (2024)- [c6]Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury:
A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c5]Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury:
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. ISCAS 2023: 1 - [c4]Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC 2023: 426-427 - [c3]Sigang Ryu, Adou Sangbone Assoa, Shota Konno, Arijit Raychowdhury:
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications. VLSI Technology and Circuits 2023: 1-2 - [c2]Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. VLSI Technology and Circuits 2023: 1-2 - 2020
- [c1]Shota Konno, Yuichi Miyahara, Kazuki Sobue, Koichi Hamashita:
A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry. A-SSCC 2020: 1-2
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