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2020 – today
- 2024
[c57]Jean-Michel Gorius
, Simon Rokicki, Steven Derrien:
A Unified Memory Dependency Framework for Speculative High-Level Synthesis. CC 2024: 13-25- [c56]Dylan Leothaud, Jean-Michel Gorius, Simon Rokicki, Steven Derrien:
Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis. FPL 2024: 109-117 - [i4]Corentin Ferry, Nicolas Derumigny, Steven Derrien, Sanjay V. Rajopadhye:
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators. CoRR abs/2401.12071 (2024) - 2023
- [j20]Corentin Ferry, Tomofumi Yuki, Steven Derrien, Sanjay V. Rajopadhye:
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1546-1559 (2023) - [c55]Louis Narmour, Steven Derrien, Sanjay V. Rajopadhye:
Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations. PACT 2023: 187-198 - [c54]Sara Sadat Hoseininasab, Caroline Collange, Steven Derrien:
Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis. ARC 2023: 19-34 - [i3]Corentin Ferry, Steven Derrien, Sanjay V. Rajopadhye:
An Irredundant Decomposition of Data Flow with Affine Dependences. CoRR abs/2312.03646 (2023) - 2022
- [j19]Jean-Michel Gorius, Simon Rokicki, Steven Derrien:
SpecHLS: Speculative Accelerator Design Using High-Level Synthesis. IEEE Micro 42(5): 99-107 (2022) - [j18]Frank Hannig, Steven Derrien:
Special Issue on Applied Reconfigurable Computing. J. Signal Process. Syst. 94(9): 847-848 (2022) - [c53]Jean-Michel Gorius, Simon Rokicki, Steven Derrien:
Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. FPT 2022: 1-6 - [i2]Corentin Ferry, Tomofumi Yuki, Steven Derrien, Sanjay V. Rajopadhye:
Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout. CoRR abs/2202.05933 (2022) - [i1]Corentin Ferry, Steven Derrien, Sanjay V. Rajopadhye:
Maximal Atomic irRedundant Sets: a Usage-based Dataflow Partitioning Algorithm. CoRR abs/2211.15933 (2022) - 2021
- [e1]Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings. Lecture Notes in Computer Science 12700, Springer 2021, ISBN 978-3-030-79024-0 [contents] - 2020
- [j17]Yohann Uguen, Florent de Dinechin, Victor Lezaud, Steven Derrien:
Application-Specific Arithmetic in High-Level Synthesis Tools. ACM Trans. Archit. Code Optim. 17(1): 5:1-5:23 (2020) - [j16]Steven Derrien, Thibaut Marty, Simon Rokicki, Tomofumi Yuki:
Toward Speculative Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 4229-4239 (2020) - [j15]Thibaut Marty, Tomofumi Yuki, Steven Derrien:
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4777-4790 (2020)
2010 – 2019
- 2019
- [j14]Simon Reder, Fabian Kempf, Harald Bucher, Jürgen Becker, Panayiotis Alefragis, Nikolaos S. Voros, Stefanos Skalistis, Steven Derrien, Isabelle Puaut, Oliver Oey, Timo Stripf, Christian Ferdinand, Clément David, Peer Ulbig, David Müller, Umut Durak:
Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. J. Aerosp. Inf. Syst. 16(11): 521-533 (2019) - [j13]Simon Rokicki, Erven Rohou, Steven Derrien:
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1872-1885 (2019) - [c52]Simon Rokicki, Erven Rohou, Steven Derrien:
Aggressive Memory Speculation in HW/SW Co-Designed Machines. DATE 2019: 332-335 - [c51]Benjamin Rouxel, Stefanos Skalistis, Steven Derrien, Isabelle Puaut:
Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures. ECRTS 2019: 25:1-25:24 - [c50]Mickaël Dardaillon, Stefanos Skalistis, Isabelle Puaut, Steven Derrien:
Reconciling Compiler Optimizations and WCET Estimation Using Iterative Compilation. RTSS 2019: 133-145 - 2018
- [c49]Thomas Lefeuvre, Imen Fassi, Christoph Cullmann, Gernot Gebhard, Emin-Koray Kasnakli, Isabelle Puaut, Steven Derrien:
Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction. DATE 2018: 925-930 - [c48]Simon Rokicki, Erven Rohou, Steven Derrien:
Supporting runtime reconfigurable VLIWs cores through dynamic binary translation. DATE 2018: 1009-1014 - [c47]Thibaut Marty, Tomofumi Yuki, Steven Derrien:
Enabling Overclocking Through Algorithm-Level Error Detection. FPT 2018: 174-181 - [c46]Isabelle Puaut, Mickaël Dardaillon, Christoph Cullmann, Gernot Gebhard, Steven Derrien:
Fine-Grain Iterative Compilation for WCET Estimation. WCET 2018: 9:1-9:12 - 2017
- [j12]Benjamin Rouxel, Steven Derrien, Isabelle Puaut:
Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures. ACM Trans. Embed. Comput. Syst. 16(5s): 164:1-164:20 (2017) - [j11]Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker:
Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. 88(2): 103-105 (2017) - [c45]Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker:
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE 2017: 286-289 - [c44]Simon Rokicki, Erven Rohou, Steven Derrien:
Hardware-accelerated dynamic binary translation. DATE 2017: 1062-1067 - [c43]Ali Hassan El Moussawi, Steven Derrien:
Superword level parallelism aware word length optimization. DATE 2017: 1068-1073 - [c42]Yohann Uguen, Florent de Dinechin, Steven Derrien:
A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. FCCM 2017: 80 - [c41]Gaël Deest, Tomofumi Yuki, Sanjay V. Rajopadhye, Steven Derrien:
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. FPL 2017: 1-8 - [c40]Yohann Uguen, Florent de Dinechin, Steven Derrien:
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. FPL 2017: 1-8 - 2016
- [c39]Ali Hassan El Moussawi, Steven Derrien:
Demo: SLP-aware word length optimization. DASIP 2016: 233-234 - [c38]Nicolas Estibals, Gaël Deest, Ali Hassan El Moussawi, Steven Derrien:
System level synthesis for virtual memory enabled hardware threads. DATE 2016: 738-743 - [c37]Baptiste Roux, Matthieu Gautier, Olivier Sentieys, Steven Derrien:
Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures. MCSoC 2016: 209-216 - 2015
- [j10]Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton, Alexandre Cornu, Dominique Lavenier:
Combining execution pipelines to improve parallel implementation of HMMER on FPGA. Microprocess. Microsystems 39(7): 457-470 (2015) - 2014
- [j9]Anne-Marie Chana, Patrice Quinton, Steven Derrien:
Component reuse methodology for multi-clock Data-Flow parallel embedded Systems. ARIMA J. 18 (2014) - [c36]Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien, Christophe Huriaux:
Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes. FCCM 2014: 230-233 - [c35]Gaël Deest, Tomofumi Yuki, Olivier Sentieys, Steven Derrien:
Toward scalable source level accuracy analysis for floating-point to fixed-point conversion. ICCAD 2014: 726-733 - 2013
- [j8]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, Thomas Perschke:
Compiling Scilab to high performance embedded multicore systems. Microprocess. Microsystems 37(8-C): 1033-1049 (2013) - [j7]Antoine Morvan, Steven Derrien, Patrice Quinton:
Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 339-352 (2013) - [c34]Mythri Alle, Antoine Morvan, Steven Derrien:
Runtime dependency analysis for loop pipelining in high-level synthesis. DAC 2013: 51:1-51:10 - [c33]Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys:
Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations. DSD 2013: 543-550 - [c32]Wuliang Sun, Benoît Combemale, Steven Derrien, Robert B. France:
Using Model Types to Support Contract-Aware Model Substitutability. ECMFA 2013: 118-133 - [c31]Tomofumi Yuki, Antoine Morvan, Steven Derrien:
Derivation of efficient FSM from loop nests. FPT 2013: 286-293 - [c30]Antoine Floch, Tomofumi Yuki, Ali El Moussawi, Antoine Morvan, Kevin J. M. Martin, Maxime Naullet, Mythri Alle, Ludovic L'Hours, Nicolas Simon, Steven Derrien, François Charot, Christophe Wolinski, Olivier Sentieys:
GeCoS: A framework for prototyping custom hardware design flows. SCAM 2013: 100-105 - 2012
- [j6]Jean-Marc Jézéquel, Benoît Combemale, Steven Derrien, Clément Guy, Sanjay V. Rajopadhye:
Bridging the chasm between MDE and the world of compilation. Softw. Syst. Model. 11(4): 581-597 (2012) - [j5]Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys:
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow. ACM Trans. Design Autom. Electr. Syst. 17(1): 2:1-2:24 (2012) - [c29]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Jordy Potman, Kim Sunesen, Steven Derrien, Olivier Sentieys, Jürgen Becker:
A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. CSE 2012: 383-390 - [c28]Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien:
A semiempirical model for wakeup time estimation in power-gated logic clusters. DAC 2012: 48-55 - [c27]Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Ménard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer:
From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD 2012: 114-121 - [c26]Clément Guy, Benoît Combemale, Steven Derrien, Jim Steel, Jean-Marc Jézéquel:
On Model Subtyping. ECMFA 2012: 400-415 - [c25]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Ménard, Olivier Sentieys, Diana Göhringer, Thomas Perschke:
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC 2012: 1-8 - [c24]George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Ménard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas:
From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS 2012: 268-275 - [c23]Patrice Quinton, Anne-Marie Chana, Steven Derrien:
Efficient hardware implementation of data-flow parallel embedded systems. ICSAMOS 2012: 364-371 - 2011
- [b1]Steven Derrien:
Contributions à la conception d'architectures matérielles dédiées. University of Rennes 1, France, 2011 - [j4]Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien:
A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters. J. Low Power Electron. 7(4): 482-489 (2011) - [c22]Alexandre Cornu, Steven Derrien, Dominique Lavenier:
HLS Tools for FPGA: Faster Development with Better Performance. ARC 2011: 67-78 - [c21]Antoine Morvan, Steven Derrien, Patrice Quinton:
Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion. FPT 2011: 1-10 - [c20]V. Basupalli, Tomofumi Yuki, Sanjay V. Rajopadhye, Antoine Morvan, Steven Derrien, Patrice Quinton, David Wonnacott:
ompVerify: Polyhedral Analysis for the OpenMP Programmer. IWOMP 2011: 37-53 - [c19]Antoine Floch, Tomofumi Yuki, Clément Guy, Steven Derrien, Benoît Combemale, Sanjay V. Rajopadhye, Robert B. France:
Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far? MoDELS 2011: 608-622 - [c18]Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien:
Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters. VLSI Design 2011: 340-345 - 2010
- [j3]Steven Derrien, Patrice Quinton:
Hardware Acceleration of HMMER on FPGAs. J. Signal Process. Syst. 58(1): 53-67 (2010) - [c17]Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys:
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. DAC 2010: 693-698 - [c16]Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys:
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. DSD 2010: 493-500 - [c15]Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton:
Accelerating HMMER on FPGA using parallel prefixes and reductions. FPT 2010: 37-44
2000 – 2009
- 2009
- [c14]Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys:
Ultra Low-power FSM for Control Oriented Applications. ISCAS 2009: 1577-1580 - 2008
- [j2]Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere:
Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. 3(3): 170-180 (2008) - 2007
- [c13]Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton:
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. ARC 2007: 247-258 - [c12]Steven Derrien, Patrice Quinton:
Parallelizing HMMER for Hardware Acceleration on FPGAs. ASAP 2007: 10-17 - 2006
- [c11]Auguste Noumsi, Steven Derrien, Patrice Quinton:
Acceleration of a content-based image-retrieval application on the RDISK cluster. IPDPS 2006 - 2005
- [j1]Stéphane Guyetant, Mathieu Giraud, Ludovic L'Hours, Steven Derrien, Stéphane Rubini, Dominique Lavenier, Frédéric Raimbault:
Cluster of re-configurable nodes for scanning large genomic banks. Parallel Comput. 31(1): 73-96 (2005) - [c10]Alain Darte, Steven Derrien, Tanguy Risset:
Hardware/Software Interface for Multi-Dimensional Processor Arrays. ASAP 2005: 28-35 - 2003
- [c9]Dominique Lavenier, Stéphane Guyetant, Steven Derrien, Stéphane Rubini:
A Reconfigurable Parallel Disk System for Filtering Genomic Banks. Engineering of Reconfigurable Systems and Algorithms 2003: 154-166 - 2002
- [c8]Sanjay V. Rajopadhye, Steven Derrien:
Energy/Power Estimation of Regular Processor Arrays. ISSS 2002: 50-55 - 2001
- [c7]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combining Instruction and Loop Level Parallelism for FPGAs. FCCM 2001: 273-282 - [c6]Steven Derrien, Sanjay V. Rajopadhye:
Loop Tiling for Reconfigurable Accelerators. FPL 2001: 398-408 - [c5]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS 2001: 165-170 - 2000
- [c4]Steven Derrien, Sanjay V. Rajopadhye:
FCCMS and the Memory Wall. FCCM 2000: 329-330 - [c3]Steven Derrien, Kurt Konolige:
Approximating a Single Viewpoint in Panoramic Imaging Devices. ICRA 2000: 3931-3938 - [c2]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC 2000: 155-159 - [c1]Steven Derrien, Tanguy Risset:
Interfacing compiled FPGA programs: the MMAlpha approach. PDPTA 2000
Coauthor Index
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last updated on 2024-10-22 21:17 CEST by the dblp team
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