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Journal Articles
- 2012
[j6]Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson:
An Overview of Static Pipelining. IEEE Comput. Archit. Lett. 11(1): 17-20 (2012)- 2005
- [j5]William C. Kreahling, David B. Whalley, Mark W. Bailey, Xin Yuan, Gang-Ryung Uh, Robert van Engelen:
Branch elimination by condition merging. Softw. Pract. Exp. 35(1): 51-74 (2005) - [j4]Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Yunheung Paek, Vincent Cao, Chris Burns:
Compiler transformations for effectively exploiting a zero overhead loop buffer. Softw. Pract. Exp. 35(4): 393-412 (2005) - 2004
- [j3]Jinhwan Kim, Yunheung Paek, Gang-Ryung Uh:
Code optimizations for a VLIW-style network processing unit. Softw. Pract. Exp. 34(9): 847-874 (2004) - 2002
- [j2]Minghui Yang, Gang-Ryung Uh, David B. Whalley:
Efficient and effective branch reordering using profile data. ACM Trans. Program. Lang. Syst. 24(6): 667-697 (2002) - 1999
- [j1]Gang-Ryung Uh, David B. Whalley:
Effectively Exploiting Indirect Jumps. Softw. Pract. Exp. 29(12): 1061-1101 (1999)
Conference and Workshop Papers
- 2023
- [c15]Abigail Mortensen, Scott Pomerville, David B. Whalley, Soner Önder, Gang-Ryung Uh:
Facilitating the Bootstrapping of a New ISA. LCTES 2023: 2-12 - 2015
- [c14]B. Davis, Ryan Baird, Peter Gavin, Magnus Själander
, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson:
Scheduling instruction effects for a statically pipelined processor. CASES 2015: 167-176 - [c13]Ryan Baird, Peter Gavin, Magnus Själander, David B. Whalley, Gang-Ryung Uh:
Optimizing Transfers of Control in the Static Pipeline Architecture. LCTES 2015: 1:1-1:10 - 2013
- [c12]Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David B. Whalley, Magnus Själander, Gary S. Tyson:
Improving processor efficiency by statically pipelining instructions. LCTES 2013: 33-44 - 2011
- [c11]Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson:
Improving Low Power Processor Efficiency with Static Pipelining. Interaction between Compilers and Computer Architectures 2011: 17-24 - 2007
- [c10]Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek:
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. CC 2007: 16-31 - 2006
- [c9]Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek:
Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs. EUC Workshops 2006: 741-754 - 2004
- [c8]Wankang Zhao, Prasad A. Kulkarni, David B. Whalley, Christopher A. Healy, Frank Mueller, Gang-Ryung Uh:
Tuning the WCET of Embedded Applications. IEEE Real-Time and Embedded Technology and Applications Symposium 2004: 472-481 - 2003
- [c7]William C. Kreahling, David B. Whalley, Mark W. Bailey, Xin Yuan, Gang-Ryung Uh, Robert van Engelen:
Branch Elimination via Multi-variable Condition Merging. Euro-Par 2003: 261-270 - [c6]Gang-Ryung Uh:
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. SCOPES 2003: 133-150 - 2002
- [c5]Jinhwan Kim, Sungjoon Jung, Yunheung Paek, Gang-Ryung Uh:
Experience with a retargetable compiler for a commercial network processor. CASES 2002: 178-187 - 2000
- [c4]Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Chris Burns, Vincent Cao:
Techniques for Effectively Exploiting a Zero Overhead Loop Buffer. CC 2000: 157-172 - 1999
- [c3]Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Chris Burns, Vincent Cao:
Effective Exploitation of a Zero Overhead Loop Buffer. Workshop on Languages, Compilers, and Tools for Embedded Systems 1999: 10-19 - 1998
- [c2]Minghui Yang, Gang-Ryung Uh, David B. Whalley:
Improving Performance by Branch Reordering. PLDI 1998: 130-141 - 1997
- [c1]Gang-Ryung Uh, David B. Whalley:
Coalescing Conditional Branches into Efficient Indirect Jumps. SAS 1997: 315-329
Coauthor Index
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