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ORCIDKensuke Iizuka
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- affiliation: Keio University, Minato, Tokyo, Japan
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2020 – today
- 2024
[j7]Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano:
Power Optimized Design Framework for FPGA Clusters. IPSJ Trans. Syst. LSI Des. Methodol. 17: 77-86 (2024)- [c15]Hideharu Amano, Kensuke Iizuka:
Power analysis of an optical interconnected FPGA cluster for roadside units. ICCE 2024: 1-2 - 2023
- [j6]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of CNN on Multi-FPGA Cluster. IEICE Trans. Inf. Syst. 106(7): 1198-1208 (2023) - [j5]M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search. IEICE Trans. Inf. Syst. 106(11): 1783-1795 (2023) - [j4]Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano:
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters. IEICE Trans. Inf. Syst. 106(12): 1997-2005 (2023) - [c14]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster. candar 2023: 100-106 - [c13]Takumi Inage, Kensuke Iizuka, Hideharu Amano:
Board Allocation Algorithm for the Resource Management System of FiC. MCSoC 2023: 218-224 - 2022
- [j3]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. IEICE Trans. Inf. Syst. 105-D(12): 2008-2018 (2022) - [c12]Kensuke Iizuka, Haruna Takagi, Aika Kamei
, Kazuei Hironaka, Hideharu Amano:
Power Analysis of Directly-connected FPGA Clusters. COOL CHIPS 2022: 1-6 - [c11]Aoi Hiruma, Kensuke Iizuka, Hideharu Amano:
Toward a training of CNNs on a multi-FPGA system. CANDARW 2022: 229-235 - [c10]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. MCSoC 2022: 45-52 - 2021
- [j2]Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano:
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). IEICE Trans. Inf. Syst. 104-D(8): 1321-1331 (2021) - [j1]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. 104-D(12): 2029-2039 (2021) - [c9]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Implementing VTA, a tensor accelerator on Flow-in-Cloud. ACIT 2021: 46-50 - [c8]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. COOL CHIPS 2021: 1-6 - [c7]Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano:
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR 2021: 95-101 - [c6]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of CNN on Multi-FPGA Cluster. MCSoC 2021: 77-83 - 2020
- [c5]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) 2020: 211-217 - [c4]Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. CANDAR (Workshops) 2020: 277-281 - [c3]Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano:
A Method of Partitioning Convolutional Layer to Multiple FPGAs. ISOCC 2020: 25-26
2010 – 2019
- 2019
- [c2]Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano:
Demonstration of Flow-in-Cloud: A Multi-FPGA System. FPL 2019: 417-418 - [c1]Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation. HEART 2019: 9:1-9:6
Coauthor Index
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