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2020 – today
- 2024
[c10]Enne Wittenhagen, Dominik Wilding, Patrick Kurth, Sebastian Linnhoff, Frowin Buballa, Urs Hecht, Patrick J. Artz, Friedel Gerfers:
An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR. ISCAS 2024: 1-5- 2023
- [c9]Patrick Kurth
, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Helia Ordouei, Friedel Gerfers:
A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling. ISCAS 2023: 1-5 - [c8]Frowin Buballa, Sebastian Linnhoff, Enne Wittenhagen, Urs Hecht, Friedel Gerfers:
A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS. NEWCAS 2023: 1-5 - [c7]Sebastian Linnhoff, Frowin Buballa, Julius Edler, Enne Wittenhagen, Urs Hecht, Friedel Gerfers:
A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold. NEWCAS 2023: 1-5 - [c6]Enne Wittenhagen, Patrick Kurth, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Nima Lotfi, Friedel Gerfers:
A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB |THD| and >49.3 dB SNDR in 22 nm FD-SOI CMOS. NEWCAS 2023: 1-4 - [c5]Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers:
A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. VLSI Technology and Circuits 2023: 1-2 - 2021
- [c4]Frowin Buballa, Sebastian Linnhoff, Michael Reinhold, Friedel Gerfers:
A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. ISCAS 2021: 1-5 - [c3]Sebastian Linnhoff, Erik Sippel, Frowin Buballa, Michael Reinhold, Martin Vossiek, Friedel Gerfers:
A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. ISCAS 2021: 1-4 - 2020
- [c2]Sebastian Linnhoff, Frowin Buballa, Michael Reinhold, Friedel Gerfers:
A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS. ICECS 2020: 1-4
2010 – 2019
- 2018
- [c1]Marcel Runge, Sebastian Linnhoff, Friedel Gerfers:
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS. MWSCAS 2018: 779-782
Coauthor Index
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