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Kwandong Kim
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2020 – today
- 2022
- [j3]Hyojun Kim
, Woosong Jung
, Kwandong Kim, Sungwoo Kim
, Woo-Seok Choi
, Deog-Kyoon Jeong
:
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. IEEE J. Solid State Circuits 57(6): 1712-1722 (2022) - [j2]Moon-Chul Choi
, Sanghee Lee, Seungha Roh, Kwangho Lee
, Jonghyun Oh
, Sungwoo Kim
, Kwandong Kim, Woo-Seok Choi
, Jaeha Kim
, Deog-Kyoon Jeong
:
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2677-2681 (2022)
2010 – 2019
- 2019
- [j1]Moon-Chul Choi
, Deog-Kyoon Jeong
, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko
, Haram Ju, Kwanseo Park
, Hyojun Kim
, Kwandong Kim:
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1927-1931 (2019) - [c1]Seong Ju Lee, Byung Deuk Jeon, Kyeong Pil Kang, Dong Yoon Ka, Na Yeon Kim, Yongseop Kim, Yunseok Hong, Mankeun Kang, Jinyong Min, Mingyu Lee, Chunseok Jeong, Kwandong Kim, Doobock Lee, Junghyun Shin, Yuntack Han, Youngbo Shim, Youngjoo Kim, Yongsun Kim, Hyunseok Kim, Jaewoong Yun, Byungsoo Kim, Seokhwan Han, Changwoo Lee, Junyong Song, Ho Uk Song, Il Park, Yongju Kim, Junhyun Chun, Jonghoon Oh:
A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller. ISSCC 2019: 384-386
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