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ORCIDSungphil Choi
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2020 – today
- 2024
[c2]Yangho Seo, Jihee Choi, Sunki Cho, Hyunwook Han, Wonjong Kim, Gyeongha Ryu, Jungil Ahn, Younga Cho, Sungphil Choi, Seohee Lee, Wooju Lee, Chaehyuk Lee, Kiup Kim, Seongseop Lee, Sangbeom Park, Minjun Choi, Sungwoo Lee, Mino Kim, Taekyun Shin, Hyeongsoo Jeong, Hyunseung Kim, Houk Song, Yunsuk Hong, Seokju Yoon, Giwook Park, Hokeun You, Changkyu Choi, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim:
13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction. ISSCC 2024: 246-248- 2023
- [j5]Yong-Un Jeong
, Sungphil Choi, Suhwan Kim, Joo-Hyung Chae:
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4793-4803 (2023) - 2022
- [j4]Yong-Un Jeong, Sungphil Choi, Joo-Hyung Chae, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim:
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1125-1134 (2022) - 2021
- [j3]Sungphil Choi, Yong-Un Jeong, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim:
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. IEEE Access 9: 120285-120296 (2021) - 2020
- [j2]Joo-Hyung Chae, Minchang Kim, Sungphil Choi, Suhwan Kim:
A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 220-224 (2020)
2010 – 2019
- 2019
- [c1]Yong-Un Jeong, Joo-Hyung Chae, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim:
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. ISLPED 2019: 1-6 - 2018
- [j1]Mino Kim, Joo-Hyung Chae, Sungphil Choi, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong, Suhwan Kim:
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1894-1898 (2018)
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