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ORCIDXiaoyu Sun 0001
Person information
- affiliation: Georgia Institute of Technology, Atlanta, GA, USA
- affiliation (former): Arizona State University, Tempe, AZ, USA
Other persons with the same name
- Xiaoyu Sun — disambiguation page
- Xiaoyu Sun 0002
![[0000-0001-7434-0452]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-7434-0452")
— Australian National University, Canberra, ACT, Australia (and 1 more) - Xiaoyu Sun 0003 — National Marine Environmental Forecasting Center, State Oceanic Administration, Beijing, China (and 1 more)
- Xiaoyu Sun 0004 — Northeastern University, Shenyang, Liaoning, China
- Xiaoyu Sun 0005 — Southeast University, Nanjing, China
- Xiaoyu Sun 0006 — Zhengzhou Xinda Institute of Advanced Technology, Zhengzhou, Henan, China (and 1 more)
- Xiaoyu Sun 0007 — Illinois Institute of Technology, Chicago, IL, USA
- Xiaoyu Sun 0008 — Neusoft Education Technology Group, Dalian, China (and 1 more)
- Xiaoyu Sun 0009 — China University of Petroleum (East China), Qingdao, China
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Journal Articles
- 2024
[j11]Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang:
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1191-1205 (2024)- 2022
- [j10]Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu:
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. IEEE J. Solid State Circuits 57(9): 2868-2877 (2022) - [j9]Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu:
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. ACM Trans. Design Autom. Electr. Syst. 27(4): 37:1-37:19 (2022) - 2021
- [j8]Bohan Lin, Yachuan Pang, Bin Gao, Jianshi Tang, Dong Wu, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, Meng-Fan Chang, He Qian, Huaqiang Wu:
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source. IEEE J. Solid State Circuits 56(5): 1641-1650 (2021) - [j7]Gauthaman Murali, Xiaoyu Sun, Shimeng Yu, Sung Kyu Lim:
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 386-396 (2021) - 2020
- [j6]Xiaoming Chen, Kai Ni, Michael T. Niemier, Dayane Reis, Xiaoyu Sun, Panni Wang, Suman Datta, Xiaobo Sharon Hu, Xunzhao Yin, Matthew Jerry, Shimeng Yu, Ann Franchesca Laguna:
The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures. IEEE Des. Test 37(1): 79-99 (2020) - [j5]Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun:
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 189-202 (2020) - 2019
- [j4]Xiaoyu Sun, Shimeng Yu:
Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 570-579 (2019) - [j3]Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim:
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro 39(6): 54-63 (2019) - [j2]Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang:
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4172-4185 (2019) - 2017
- [j1]Xiaoyu Sun, Rui Liu, Yi-Ju Chen, Hsiao-Yun Chiu, Wei-Hao Chen, Meng-Fan Chang, Shimeng Yu:
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2962-2965 (2017)
Conference and Workshop Papers
- 2021
- [c15]Wantong Li, Shanshi Huang, Xiaoyu Sun, Hongwu Jiang, Shimeng Yu:
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. CICC 2021: 1-2 - [c14]Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu:
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSCIRC 2021: 79-82 - [c13]Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu:
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSDERC 2021: 79-82 - [c12]Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo:
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. IRPS 2021: 1-7 - 2020
- [c11]Shimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang:
Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects. CICC 2020: 1-4 - [c10]Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu:
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. DATE 2020: 1025-1030 - 2019
- [c9]Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang:
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC 2019: 396-398 - [c8]Yachun Pang, Bin Gao, Dong Wu, Shengyu Yi, Qi Liu, Wei-Hao Chen, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, He Qian, Meng-Fan Chang, Huaqiang Wu:
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate. ISSCC 2019: 402-404 - [c7]Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu:
Inference engine benchmarking across technological platforms from CMOS to RRAM. MEMSYS 2019: 471-479 - 2018
- [c6]Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu:
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC 2018: 574-579 - [c5]Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu:
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. DAC 2018: 21:1-21:6 - [c4]Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu:
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE 2018: 1423-1428 - [c3]Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang:
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498 - [c2]Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, Chaitali Chakrabarti:
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. SiPS 2018: 13-18 - [c1]Manqing Mao, Xiaoyu Sun, Xiaochen Peng, Shimeng Yu, Chaitali Chakrabarti:
A Versatile ReRAM-based Accelerator for Convolutional Neural Networks. SiPS 2018: 211-216
Informal and Other Publications
- 2019
- [i1]Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo:
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. CoRR abs/1909.07514 (2019)
Coauthor Index
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