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Minhan Chen
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2020 – today
- 2024
- [c4]Ping Lu, Minhan Chen, Shaishav Desai:
A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC. ISCAS 2024: 1-5 - 2023
- [c3]Ping Lu, Bupesh Pandita, Minhan Chen:
Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface. MWSCAS 2023: 614-618 - 2022
- [c2]Ping Lu, Charlie Boecker, Bupesh Pandita, Minhan Chen, Sheethal Nayak:
A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET. ISCAS 2022: 1714-1718 - [c1]Ping Lu, Minhan Chen, Shaishav Desai:
An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications. MWSCAS 2022: 1-4
1990 – 1999
- 1998
- [j1]Minhan Chen, Wolfgang Porod:
Simulation of Quantum-Dot Structures in Si/SiO2. VLSI Design 6(1-4): 335-339 (1998)
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