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Gustavo M. Santana
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2020 – today
- 2021
- [j3]Guilherme da Costa Ferreira, Guilherme Paim, Leandro M. G. Rocha, Gustavo M. Santana, Renato H. Neuenfeld, Eduardo A. C. da Costa, Sergio Bampi:
Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors. IET Comput. Digit. Tech. 15(3): 230-240 (2021) - 2020
- [j2]Guilherme Paim, Gustavo M. Santana, Brunno A. Abreu, Leandro M. G. Rocha, Mateus Grellert, Eduardo A. C. da Costa, Sergio Bampi:
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding. J. Real Time Image Process. 17(5): 1735-1754 (2020)
2010 – 2019
- 2019
- [j1]Guilherme Paim, Leandro Mateus Giacomini Rocha, Gustavo Madeira Santana, Leonardo Bandeira Soares, Eduardo Antonio Cesar da Costa, Sergio Bampi:
Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 680-693 (2019) - 2018
- [c4]Luis F. Sequeira, Gustavo M. Santana, Guilherme Paim, Leandro M. G. Rocha, Brunno Abreu, Eduardo Costa, Sergio Bampi:
Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors. NEWCAS 2018: 309-312 - [c3]Brunno Abreu, Gustavo M. Santana, Mateus Grellert, Guilherme Paim, Leandro M. G. Rocha, Eduardo A. C. da Costa, Sergio Bampi:
Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation. SBCCI 2018: 1-6 - 2017
- [c2]Gustavo M. Santana, Guilherme Paim, Leandro M. G. Rocha, Renato Neuenfeld, Mateus Beck Fonseca, Eduardo A. C. da Costa, Sergio Bampi:
Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors. ICECS 2017: 486-489 - [c1]Leandro M. G. Rocha, Guilherme Paim, Gustavo M. Santana, Brunno A. Abreu, Rafael Ferreira, Eduardo A. C. da Costa, Sergio Bampi:
Physical implementation of an ASIC-oriented SRAM-based viterbi decoder. ICECS 2017: 526-529
Coauthor Index
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