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K. Bharath
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2020 – today
- 2023
- [j2]Mahendra Rathor
, Aditya Anshul
, K. Bharath, Rahul Chaurasia
, Anirban Sengupta:
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. Comput. Electr. Eng. 105: 108476 (2023) - [j1]Anirban Sengupta, Rahul Chaurasia
, K. Bharath:
Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs. Comput. Electr. Eng. 111(Part A): 108928 (2023) - 2022
- [c3]Aditya Anshul
, K. Bharath, Anirban Sengupta:
Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems. iSES 2022: 95-100
2010 – 2019
- 2017
- [c2]Harsh Rawat, K. Bharath, Alexander Fell
:
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. SoCC 2017: 1-6 - 2016
- [c1]Pulkit Sharma, R. Anusha, K. Bharath, Jasmine Kaur Gulati, Preet K. Walia, Sumit Jagdish Darak
:
Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell. VDAT 2016: 1-2
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