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2020 – today
- 2023
[j3]Jinyang Guo, Lu Zhang, José Romero Hung, Chao Li, Jieru Zhao, Minyi Guo:
FPGA sharing in the cloud: a comprehensive analysis. Frontiers Comput. Sci. 17(5): 175106 (2023)- 2022
- [c14]Jiuchen Shi, Kaihua Fu, Quan Chen, Changpeng Yang, Pengfei Huang, Mosong Zhou, Jieru Zhao, Chen Chen, Minyi Guo:
Characterizing and orchestrating VM reservation in geo-distributed clouds to improve the resource efficiency. SoCC 2022: 94-109 - [c13]Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo:
SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences. DAC 2022: 571-576 - [c12]Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian:
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs. DATE 2022: 1341-1346 - [c11]Haowei Huang, Pu Pang, Quan Chen, Jieru Zhao, Wenli Zheng, Minyi Guo:
CSC: Collaborative System Configuration for I/O-Intensive Applications in Multi-Tenant Clouds. IPDPS 2022: 1327-1337 - [i6]Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian:
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs. CoRR abs/2201.10114 (2022) - [i5]Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo:
SALO: An Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences. CoRR abs/2206.14550 (2022) - [i4]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. CoRR abs/2210.08682 (2022) - 2021
- [c10]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD 2021: 1-9 - [c9]Han Zhao, Weihao Cui, Quan Chen, Jieru Zhao, Jingwen Leng, Minyi Guo:
Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks. ICCD 2021: 290-298 - [c8]Weihao Cui, Han Zhao, Quan Chen, Ningxin Zheng, Jingwen Leng, Jieru Zhao, Zhuo Song, Tao Ma, Yong Yang, Chao Li, Minyi Guo:
Enable simultaneous DNN services based on deterministic operator overlap and precise latency prediction. SC 2021: 15 - 2020
- [j2]Jieru Zhao
, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1428-1441 (2020) - [c7]Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. ASP-DAC 2020: 574-580 - [c6]Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen:
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL 2020: 269-276 - [i3]Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen:
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR abs/2006.03250 (2020) - [i2]Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. CoRR abs/2009.00871 (2020)
2010 – 2019
- 2019
- [c5]Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC 2019: 1 - [c4]Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE 2019: 1130-1135 - [c3]Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA 2019: 188 - [c2]Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang:
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD 2019: 1-6 - [i1]Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR abs/1905.03852 (2019) - 2018
- [j1]Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang:
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2555-2566 (2018) - 2017
- [c1]Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. ICCAD 2017: 430-437
Coauthor Index
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last updated on 2023-03-26 01:26 CET by the dblp team
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