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ORCIDJincheng Yang
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j11]Luhao Zhang
, Jincheng Yang, Rui Gao:
Optimal Robust Policy for Feature-Based Newsvendor. Manag. Sci. 70(4): 2315-2329 (2024)- [c4]Haoyu Zhen, Xiaowen Qiu, Peihao Chen, Jincheng Yang, Xin Yan, Yilun Du, Yining Hong, Chuang Gan:
3D-VLA: A 3D Vision-Language-Action Generative World Model. ICML 2024 - [i3]Haoyu Zhen, Xiaowen Qiu, Peihao Chen, Jincheng Yang, Xin Yan, Yilun Du, Yining Hong, Chuang Gan:
3D-VLA: A 3D Vision-Language-Action Generative World Model. CoRR abs/2403.09631 (2024) - [i2]Jincheng Yang, Lishun Wang, Miao Cao, Huan Wang, Yinping Zhao, Xin Yuan:
Coarse-Fine Spectral-Aware Deformable Convolution For Hyperspectral Image Reconstruction. CoRR abs/2406.12703 (2024) - 2023
- [j10]Xiao Han, Shiwen Chen, Meng Chen, Jincheng Yang:
Radar specific emitter identification based on open-selective kernel residual network. Digit. Signal Process. 134: 103913 (2023) - [j9]Jincheng Yang, Shiwen Chen, Jinpeng Dong, Xiao Han:
A fast Wigner Hough transform algorithm for parameter estimation of low probability of intercept radar polyphase coded signals. IET Signal Process. 17(5) (2023) - [j8]Lingxiang Wei, Dongjun Guo, Zhilong Chen, Jincheng Yang, Tianliu Feng:
Forecasting Short-Term Passenger Flow of Subway Stations Based on the Temporal Pattern Attention Mechanism and the Long Short-Term Memory Network. ISPRS Int. J. Geo Inf. 12(1): 25 (2023) - [j7]Alexis F. Vasseur, Jincheng Yang:
Boundary Vorticity Estimates for Navier-Stokes and Application to the Inviscid Limit. SIAM J. Math. Anal. 55(4): 3081-3107 (2023) - 2022
- [i1]Luhao Zhang, Jincheng Yang, Rui Gao:
A Simple Duality Proof for Wasserstein Distributionally Robust Optimization. CoRR abs/2205.00362 (2022) - 2021
- [j6]Ruiying Liao, Linghui Yang, Luyao Ma, Jincheng Yang, Jigui Zhu:
A Dense 3-D Point Cloud Measurement Based on 1-D Background-Normalized Fourier Transform. IEEE Trans. Instrum. Meas. 70: 1-12 (2021)
2010 – 2019
- 2019
- [j5]Jincheng Yang, Zhao Zhang, Nan Qi, Liyuan Liu, Jian Liu, Nanjian Wu:
A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. Sci. China Inf. Sci. 62(6): 62405:1-62405:16 (2019) - [j4]Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu:
0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. IET Circuits Devices Syst. 13(7): 1071-1077 (2019) - [j3]Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu:
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3733-3746 (2019) - 2018
- [j2]Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 933-944 (2018) - [c3]Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu:
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. A-SSCC 2018: 227-230 - 2017
- [j1]Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter. IEICE Electron. Express 14(11): 20170422 (2017) - [c2]Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique. A-SSCC 2017: 249-252 - 2015
- [c1]Jincheng Yang, Zhao Zhang, Peng Feng, Liyuan Liu, Nanjian Wu:
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. ASICON 2015: 1-4
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