BibTeX records: Cheolmin Park

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  author    = {Seongkwan Lee and
               Minho Kang and
               Cheolmin Park and
               HyungSun Ryu and
               Jaemoo Choi and
               Byunghyun Yim},
  title     = {3.5Gsps {MIPI} {C-PHY} Receiver Circuit for Automatic Test Equipment},
  booktitle = {{ITC}},
  pages     = {294--298},
  publisher = {{IEEE}},
  year      = {2021}
  author    = {Ki{-}Hong Kim and
               Giyoung Song and
               Cheolmin Park and
               Kwang{-}Seok Yun},
  title     = {Multifunctional Woven Structure Operating as Triboelectric Energy
               Harvester, Capacitive Tactile Sensor Array, and Piezoresistive Strain
               Sensor Array},
  journal   = {Sensors},
  volume    = {17},
  number    = {11},
  pages     = {2582},
  year      = {2017}
  author    = {Reid J. Riedlinger and
               Ron Arnold and
               Larry Biro and
               William J. Bowhill and
               Jason Crop and
               Kevin Duda and
               Eric S. Fetzer and
               Olivier Franza and
               Tom Grutkowski and
               Casey Little and
               Charles Morganti and
               Gary Moyer and
               Ashley Munch and
               Mahalingam Nagarajan and
               Cheolmin Park and
               Christopher Poirier and
               Bill Repasky and
               Edi Roytman and
               Tejpal Singh and
               Matthew W. Stefaniw},
  title     = {A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium{\textregistered}
               Processor for Mission-Critical Servers},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {47},
  number    = {1},
  pages     = {177--193},
  year      = {2012}
  author    = {Cheolmin Park and
               Roy Badeau and
               Larry Biro and
               Jonathan Chang and
               Tejpal Singh and
               Jim Vash and
               Bo Wang and
               Tom Wang},
  title     = {A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon{\textregistered}
  booktitle = {{ISSCC}},
  pages     = {180--181},
  publisher = {{IEEE}},
  year      = {2010}
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