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ORCIDXiao Hu 0007
Person information
- affiliation: Nanjing University, School of Electronic Science and Engineering, Nanjing, China
Other persons with the same name
- Xiao Hu — disambiguation page
- Xiao Hu 0001
![[0000-0003-3994-0385]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-3994-0385")
— University of Hong Kong, Faculty of Education, Hong Kong (and 2 more) - Xiao Hu 0002 — University of California, Los Angeles, Department of Neurosurgery, David Geffen School of Medicine, CA, USA
- Xiao Hu 0003 — Nanyang Technological University, School of Materials Science and Engineering, Singapore (and 2 more)
- Xiao Hu 0004 — Purdue University, West Lafayette, IN, USA
- Xiao Hu 0005 — University of Waterloo, Canada (and 2 more)
- Xiao Hu 0006 — Beijing Bytedance Network Technology Co., Ltd., Beijing, China (and 1 more)
- Xiao Hu 0008 — University of Ottawa, Faculty of Engineering, Ottawa, ON, Canada
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2020 – today
- 2024
[j6]Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu:
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 645-657 (2024)- 2023
- [j5]Minghao Li, Jing Tian, Xiao Hu, Zhongfeng Wang:
Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2540-2551 (2023) - [j4]Yifeng Song, Xiao Hu, Jing Tian, Zhongfeng Wang:
A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 241-252 (2023) - [j3]Xiao Hu, Jing Tian, Minghao Li, Zhongfeng Wang:
AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 719-732 (2023) - [j2]Yue Geng, Xiao Hu, Minghao Li, Zhongfeng Wang:
Rethinking Parallel Memory Access Pattern in Number Theoretic Transform Design. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1689-1693 (2023) - 2022
- [j1]Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang:
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1691-1704 (2022) - [c5]Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang:
High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber. APCCAS 2022: 1-5 - 2021
- [c4]Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang:
DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography. ASAP 2021: 175-178 - [c3]Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang:
High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol. ISCAS 2021: 1-5 - 2020
- [c2]Xiao Hu, Jing Tian, Zhongfeng Wang:
Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference. APCCAS 2020: 141-144 - [c1]Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang:
A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography. ISVLSI 2020: 334-339
Coauthor Index
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