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S. Saravanan 0004

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affiliation: K.S.R. College of Technology, Tiruchengode, India

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2010
[c1]
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S. Saravanan, M. Madheswaran:
Design and analysis of a hybrid encoded low power multiplier with reduced transition activity technique. ICWET 2010: 986-990

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2010
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S. Saravanan, M. Madheswaran:
Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme. CoRR abs/1001.1976 (2010)

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