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K. S. Vasundara Patel

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Journal Articles

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2021
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A. Rajagopal, K. Karibasappa, K. S. Vasundara Patel:
Hardware implementation of a modified SSD LDPC decoder. Int. J. Comput. Aided Eng. Technol. 14(3): 426-440 (2021)
2020
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A. Rajagopal, K. Karibasappa, K. S. Vasundara Patel:
Study of LDPC decoders with quadratic residue sequence for communication system. Int. J. Inf. Comput. Secur. 13(1): 18-31 (2020)

Conference and Workshop Papers

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2012
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G. N. Sowmya, K. S. Vasundara Patel, Rajani Rao:
Modeling of Sigma-Delta ADC with High Resolution Decimation Filter. SPIT 2012: 95-100
2011
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K. S. Vasundara Patel, K. S. Gurumurthy:
Design of High Performance Quaternary Adders. ISMVL 2011: 22-26
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Varun Vasudevan, Vinay Sheshadri, Sivarama Krishnan R., K. S. Vasundara Patel:
Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain. ISVLSI 2011: 307-312
2009
[c1]
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K. S. Vasundara Patel, K. S. Gurumurthy:
Moving From Binary Towards Multi-valued logic. CDES 2009: 24-30

Informal and Other Publications

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2010
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K. S. Vasundara Patel, K. S. Gurumurthy:
Arithmetic Operations in Multi-Valued Logic. CoRR abs/1003.5442 (2010)

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