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ORCIDYang Su 0003
Person information
- affiliation: Engineering University of People's Armed Police, Xi'an, China
Other persons with the same name
- Yang Su — disambiguation page
- Yang Su 0001
![[0000-0002-4157-0021]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-4157-0021")
— University of Adelaide, Adelaide, SA, Australia - Yang Su 0002 — Jilin University, Changchun, Jilin, China
- Yang Su 0004 — Nanjing University of Aeronautics and Astronautics, Nanjing, China
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2020 – today
- 2025
[j14]Jianfei Wang, Chen Yang, Yishuo Meng, Fahong Zhang, Jia Hou, Siwei Xiang, Yang Su:
A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 72(3): 1358-1371 (2025)- [j13]Jianfei Wang, Chen Yang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Leibo Liu:
A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. IEEE Trans. Circuits Syst. II Express Briefs 72(1): 243-247 (2025) - [j12]Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang:
An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 72(1): 248-252 (2025) - [j11]Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang:
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. IEEE Trans. Very Large Scale Integr. Syst. 33(2): 588-592 (2025) - [j10]Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang:
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. IEEE Trans. Very Large Scale Integr. Syst. 33(5): 1457-1461 (2025) - [c7]Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang:
Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. ASP-DAC 2025: 1302-1307 - 2024
- [j9]Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su:
A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 359-372 (2024) - [j8]Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su:
A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2344-2348 (2024) - [j7]Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang:
A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography. IEEE Trans. Circuits Syst. II Express Briefs 71(12): 5004-5008 (2024) - [c6]Songyin Zhao, Yang Su:
Sitting Posture Recognition Based on the Computer's Camera. CVIPPR 2024: 30 - 2023
- [j6]Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Yang Su:
TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1153-1166 (2023) - 2022
- [j5]Yang Su, Bai-Long Yang, Chen Yang, Songyin Zhao:
ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2857-2870 (2022) - [j4]Yang Su, Bai-Long Yang, Chen Yang, Zepeng Yang, Yi-Wei Liu:
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 993-1006 (2022) - 2021
- [j3]Yang Su, Bai-Long Yang, Chen Yang, Jing-Yuan He:
High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor. J. Ambient Intell. Humaniz. Comput. 12(7): 7727-7743 (2021) - [c5]Chen Yang, Zepeng Yang, Jia Hou, Yang Su:
A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference. ICECS 2021: 1-4 - 2020
- [j2]Yang Su, Bailong Yang, Chen Yang, Luogeng Tian:
FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption. IEEE Access 8: 168008-168025 (2020) - [c4]Luogeng Tian, Bailong Yang, Xinli Yin, Yang Su:
A Survey of Personalized Recommendation Based on Machine Learning Algorithms. EITCE 2020: 602-610
2010 – 2019
- 2019
- [j1]Yang Su, Junwei Shen, Min-Qing Zhang:
A high security and efficiency protection of confidentiality and integrity for off-chip memory. J. Ambient Intell. Humaniz. Comput. 10(7): 2633-2643 (2019)
2000 – 2009
- 2009
- [c3]Xuanwu Zhou, Yang Su, Ping Wei:
Further Study on Proxy Authorization and Its Scheme. Complex (2) 2009: 1701-1718 - 2008
- [c2]Yang Su, Xuan-Wu Zhou, Min-Qing Zhang:
Research on Modeling Traversing Features in Concurrent Software System. CSSE (2) 2008: 81-84 - [c1]Yang Su, Xuan-Wu Zhou, Min-Qing Zhang:
Approach on Aspect-Oriented Software Reverse Engineering at Requirements Level. CSSE (2) 2008: 321-324
Coauthor Index
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