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Ravishankar Rao
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Journal Articles
- 2009
- [j5]Ravishankar Rao, Sarma B. K. Vrudhula:
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1559-1572 (2009) - 2007
- [j4]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy optimal speed control of a producer-consumer device pair. ACM Trans. Embed. Comput. Syst. 6(4): 30 (2007) - 2006
- [j3]John Y. Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella:
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications. J. Embed. Comput. 2(2): 157-166 (2006) - [j2]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy-Optimal Speed Control of a Generic Device. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2737-2746 (2006) - 2003
- [j1]Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov:
Battery Modeling for Energy-Aware System Design. Computer 36(12): 77-87 (2003)
Conference and Workshop Papers
- 2009
- [c17]Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha:
Throughput optimal task allocation under thermal constraints for multi-core processors. DAC 2009: 776-781 - 2008
- [c16]Ravishankar Rao, Sarma B. K. Vrudhula:
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. ICCAD 2008: 537-542 - [c15]Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski:
Analytical results for design space exploration of multi-core processors employing thread migration. ISLPED 2008: 229-232 - 2007
- [c14]Ravishankar Rao, Sarma B. K. Vrudhula:
Performance optimal processor throttling under thermal constraints. CASES 2007: 257-266 - [c13]Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti:
Throughput of multi-core processors under thermal constraints. ISLPED 2007: 201-206 - 2006
- [c12]John Y. Oliver
, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong
, Venkatesh Akella:
Tile size selection for low-power tile-based architectures. Conf. Computing Frontiers 2006: 83-94 - [c11]Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella:
Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. HiPC 2006: 123-134 - [c10]Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang:
An optimal analytical solution for processor speed control with thermal constraints. ISLPED 2006: 292-297 - 2005
- [c9]Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang:
An efficient combinationality check technique for the synthesis of cyclic combinational circuits. ASP-DAC 2005: 212-215 - [c8]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy optimal speed control of devices with discrete speed sets. DAC 2005: 901-904 - [c7]Ravishankar Rao, Sarma B. K. Vrudhula:
Battery optimization vs energy optimization: which to choose and when? ICCAD 2005: 439-445 - 2004
- [c6]Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan:
Disk drive energy optimization for audio-video applications. CASES 2004: 93-103 - [c5]Ravishankar Rao, Sarma B. K. Vrudhula:
Energy optimization for a two-device data flow chain. ICCAD 2004: 268-274 - [c4]John Y. Oliver
, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong:
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ISCA 2004: 150-161 - 2003
- [c3]Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov:
Analysis of discharge techniques for multiple battery systems. ISLPED 2003: 44-47 - [c2]John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong:
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. PACS 2003: 73-85 - 2002
- [c1]Ravishankar Rao, Mark Oskin, Frederic T. Chong
:
HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space. HiPC 2002: 620-629
Coauthor Index
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