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Wei-Siang Su

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2010 – 2019

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2016
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  - journals/tvlsi/ChungSL16
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  - https://dblp.org/rec/journals/tvlsi/ChungSL16
Ching-Che Chung, Wei-Siang Su, Chi-Kuang Lo:
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 408-412 (2016)
2013
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Ching-Che Chung, Duo Sheng, Wei-Siang Su:
A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices. VLSI-DAT 2013: 1-4

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