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Reza Sharafinejad

Seyyed Reza Sharafinejad

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Journal Articles

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2019
[j2]
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  - journals/tcad/AlizadehS19
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  - https://dblp.org/rec/journals/tcad/AlizadehS19
Bijan Alizadeh, Seyyed Reza Sharafinejad:
Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 245-252 (2019)
2018
[j1]
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Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi:
Automatic Correction of Dynamic Power Management Architecture in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 308-318 (2018)

Conference and Workshop Papers

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2015
[c1]
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Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita:
UPF-based formal verification of low power techniques in modern processors. VTS 2015: 1-6

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