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Subhasis Chattopadhyay
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2020 – today
- 2024
- [j3]Tanay Dey
, Purba Bhattacharya, Supratik Mukhopadhyay, Nayana Majumdar, Abhishek Seal, Subhasis Chattopadhyay:
Parallelization of Garfield++ and neBEM to simulate space-charge effects in RPCs. Comput. Phys. Commun. 294: 108944 (2024)
2010 – 2019
- 2017
- [j2]Swagata Mandal, Rourab Paul
, Suman Sau, Amlan Chakrabarti
, Subhasis Chattopadhyay
:
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. Microprocess. Microsystems 51: 313-330 (2017) - 2016
- [j1]Swagata Mandal
, Rourab Paul
, Suman Sau, Amlan Chakrabarti
, Subhasis Chattopadhyay
:
A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code. IEEE Embed. Syst. Lett. 8(4): 65-68 (2016) - 2015
- [c2]Swagata Mandal, Suman Sau, Amlan Chakrabarti
, Sushanta Kumar Pal, Subhasish Chattopadhyay
:
FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code. ATS 2015: 169-174 - [c1]Swagata Mandal, Suman Sau, Amlan Chakrabarti
, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay
:
FPGA Based Novel High Speed DAQ System Design with Error Correction. ISVLSI 2015: 80-85 - [i4]Swagata Mandal, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
FPGA based High Speed Data Acquisition System for High Energy Physics Application. CoRR abs/1503.08819 (2015) - [i3]Suman Sau, Swagata Mandal, Jogender Saini, Amlan Chakrabarti, Subhasis Chattopadhyay:
High speed fault tolerant secure communication for muon chamber using fpga based gbt emulator. CoRR abs/1505.04569 (2015) - [i2]Swagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay:
FPGA based Novel High Speed DAQ System Design with Error Correction. CoRR abs/1507.01777 (2015) - [i1]Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay:
A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code. CoRR abs/1509.06891 (2015)
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