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2010 – 2019
- 2015
[j7]Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh
:
Design and analysis of a mesh-based wireless network-on-chip. J. Supercomput. 71(8): 2830-2846 (2015)- 2014
- [j6]Chifeng Wang, Nader Bagherzadeh:
Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip. Microprocess. Microsystems 38(4): 304-315 (2014) - 2013
- [j5]Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh:
Scalable load balancing congestion-aware Network-on-Chip router architecture. J. Comput. Syst. Sci. 79(4): 421-439 (2013) - 2012
- [j4]Abdulaziz Alhussien, Chifeng Wang, Nader Bagherzadeh:
Design and evaluation of a high throughput robust router for network-on-chip. IET Comput. Digit. Tech. 6(3): 173-179 (2012) - [j3]Chifeng Wang, Nader Bagherzadeh:
High-throughput differentiated service provision router architecture for wireless network-on-chip. Int. J. High Perform. Syst. Archit. 4(1): 38-56 (2012) - [j2]Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh:
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. Microprocess. Microsystems 36(7): 555-570 (2012) - [c5]Chifeng Wang, Nader Bagherzadeh:
Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip. PDP 2012: 457-464 - [c4]Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh:
Design and Analysis of a Mesh-based Wireless Network-on-Chip. PDP 2012: 483-490 - 2011
- [j1]Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh:
Area and power-efficient innovative congestion-aware Network-on-Chip architecture. J. Syst. Archit. 57(1): 24-38 (2011) - [c3]Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh:
A Wireless Network-on-Chip Design for Multicore Platforms. PDP 2011: 409-416 - 2010
- [c2]Abdulaziz Alhussien, Chifeng Wang, Nader Bagherzadeh:
A scalable delay insensitive asynchronous NoC with adaptive routing. ICT 2010: 995-1002 - [c1]Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh:
Area and Power-efficient Innovative Network-on-Chip Architecurte. PDP 2010: 533-539
Coauthor Index
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