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Babita Jajodia
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2020 – today
- 2022
- [c8]Vishesh Mishra
, Divy Pandey, Saurabh Singh
, Sagar Satapathy, Kaustav Goswami, Babita Jajodia, Dip Sankar Banerjee:
ART-MAC: Approximate Rounding and Truncation based MAC Unit for Fault-Tolerant Applications. ISCAS 2022: 1640-1644 - [c7]Monalisa Das, Babita Jajodia:
Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA. ISOCC 2022: 65-66 - [c6]Monalisa Das, Babita Jajodia:
FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives. ISOCC 2022: 81-82 - [c5]Divy Pandey, Vishesh Mishra
, Saurabh Singh
, Sagar Satapathy, Babita Jajodia, Dip Sankar Banerjee
:
HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications. ISQED 2022: 1-5 - [c4]Saurabh Singh
, Vishesh Mishra
, Sagar Satapathy, Divy Pandey, Kaustav Goswami, Dip Sankar Banerjee
, Babita Jajodia:
EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification. ISQED 2022: 1-7 - [c3]Palak Yash, Mansi Thakare, Babita Jajodia:
Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA. LASCAS 2022: 1-4 - 2021
- [c2]Mansi Thakare, Palak Yash, Debaleena Chakraborty, Babita Jajodia:
Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA. MWSCAS 2021: 373-376 - [i1]Aman Chandra, Jitesh Lalwani, Babita Jajodia:
Towards an Optimal Hybrid Algorithm for EV Charging Stations Placement using Quantum Annealing and Genetic Algorithms. CoRR abs/2111.01622 (2021)
2010 – 2019
- 2018
- [j1]Babita Jajodia, Anil Mahanta, Shaik Rafi Ahamed:
Mixed-signal demodulator for IEEE 802.15.6 IR-UWB WBAN energy detection-based receiver. IET Circuits Devices Syst. 12(5): 523-531 (2018) - 2014
- [c1]Shaik Rafi Ahamed, Babita Jajodia, Anil Mahanta:
A Six-Segment SRRC Pulse Generator for IEEE 802.15.6 WBAN Standard. BODYNETS 2014
Coauthor Index
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last updated on 2024-05-08 21:43 CEST by the dblp team
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