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ORCIDNader Rafla 0001
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- affiliation: Boise State University, Electrical and Computer Engineering Department, ID, USA
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2020 – today
- 2023
[j4]Michael R. Wasef
, Nader Rafla:
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2497-2510 (2023)- 2022
- [j3]Luka Daoud, Nader Rafla:
Efficient mitigation technique for Black Hole router attack in Network-on-Chip. Microprocess. Microsystems 94: 104658 (2022) - [c18]Luka Daoud, Nader Rafla:
Energy-Efficient Black Hole Router Detection in Network-on-Chip. SOCC 2022: 1-6 - 2021
- [c17]Michael R. Wasef, Nader Rafla:
Hardware implementation of Multi-Rate input SoftMax activation function. MWSCAS 2021: 783-786 - 2020
- [j2]Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla:
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching. Microprocess. Microsystems 72 (2020) - [j1]Fady Hussein, Luka Daoud, Nader Rafla:
A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA. Microprocess. Microsystems 74: 103014 (2020) - [c16]Michael R. Wasef, Nader Rafla:
HLS Implementation of Linear Discriminant Analysis Classifier. ISCAS 2020: 1-4 - [c15]Eric G. Booth, Jake Carns, Casey Kennington, Nader Rafla:
Evaluating and Improving Child-Directed Automatic Speech Recognition. LREC 2020: 6340-6345 - [i1]Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla:
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching, . CoRR abs/2012.09666 (2020)
2010 – 2019
- 2019
- [c14]Luka Daoud, Fady Hussein, Nader Rafla:
Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS). CATA 2019: 36-44 - [c13]Luka Daoud, Nader Rafla:
Analysis of Black Hole Router Attack in Network-on-Chip. MWSCAS 2019: 69-72 - [c12]Luka Daoud, Nader Rafla:
Detection and prevention protocol for black hole attack in network-on-chip. NOCS 2019: 22:1-22:2 - [c11]Luka Daoud, Nader Rafla:
Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip. SoCC 2019: 266-271 - 2018
- [c10]Fady Hussein, Luka Daoud, Nader Rafla:
HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only). FPGA 2018: 293 - [c9]Luka Daoud, Muhammad Kamran Latif, Nader Rafla:
SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only). FPGA 2018: 294 - [c8]Luka Daoud, Nader Rafla:
Routing Aware and Runtime Detection for Infected Network-on-Chip Routers. MWSCAS 2018: 775-778 - [c7]Muhammad Kamran Latif, H. S. Jacinto, Luka Daoud, Nader Rafla:
Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol. MWSCAS 2018: 984-987 - [c6]Luka Daoud, Fady Hussein, Nader Rafla:
Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration. MWSCAS 2018: 1082-1085 - 2017
- [c5]H. S. Jacinto, Luka Daoud, Nader Rafla:
High level synthesis using vivado HLS for optimizations of SHA-3. MWSCAS 2017: 563-566 - 2016
- [c4]Danyal Mohammadi, Luka Daoud, Nader Rafla, Said Ahmed-Zaid:
Zynq-based SoC implementation of an induction machine control algorithm. MWSCAS 2016: 1-4 - 2015
- [c3]Danyal Mohammadi, Said Ahmed-Zaid, Nader Rafla:
Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only). FPGA 2015: 276 - 2013
- [c2]Nicholas Pauly, Nader I. Rafla:
An automated embedded computer vision system for object measurement. MWSCAS 2013: 1108-1111 - 2012
- [c1]Nader Rafla, Mohamad Sawan, José M. de la Rosa:
Welcome to the 55th IEEE international midwest symposium on circuits and systems (MWSCAS 2012). MWSCAS 2012: 1
Coauthor Index
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