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ORCIDAbdessamad Klilou
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2020 – today
- 2023
[j6]Smail Bariko
, Assia Arsalane, Abdessamad Klilou, Abdelouahed Abounada:
Efficient parallel implementation of Gaussian Mixture Model background subtraction algorithm on an embedded multi-core Digital Signal Processor. Comput. Electr. Eng. 110: 108827 (2023)- [j5]Mohamed Lamane, Mohamed Tabaa, Abdessamad Klilou:
New Approach Based on Pix2Pix-YOLOv7 mmWave Radar for Target Detection and Classification. Sensors 23(23): 9456 (2023) - 2022
- [j4]Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini:
Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. Comput. Electr. Eng. 102: 108294 (2022) - [c3]Mohamed Lamane, Mohamed Tabaa, Abdessamad Klilou:
Classification of targets detected by mmWave radar using YOLOv5. FNC/MobiSPC/SEIT 2022: 426-431 - [c2]Mohamed Lamane, Mohamed Tabaa, Abdessamad Klilou:
Optimization of mmWave radar image classification by YOLOv7 using the Pix2pix architecture. ICM 2022: 274-277 - 2021
- [j3]Abdessamad Klilou, Assia Arsalane, Mohamed Najoui, Said Belkouch:
An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP. Microprocess. Microsystems 85: 104302 (2021)
2010 – 2019
- 2018
- [j2]Assia Arsalane, Noureddine El Barbri, Abdelmoumen Tabyaoui, Abdessamad Klilou, Karim Rhofir, Abdellah Halimi:
An embedded system based on DSP platform and PCA-SVM algorithms for rapid beef meat freshness prediction and identification. Comput. Electron. Agric. 152: 385-392 (2018) - 2015
- [c1]Abdessamad Klilou, François Bourzeix, Omar Bourja, Yahya Zennayi, Lhoussein Mabrouk, Said Belkouch:
Real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors. ISDA 2015: 183-188 - 2014
- [j1]Abdessamad Klilou, Said Belkouch, Philippe Elleaume, Philippe Le Gall, François Bourzeix, Moha M'rabet Hassani:
Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect. EURASIP J. Adv. Signal Process. 2014: 161 (2014)
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