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Journal Articles
- 2020
[j5]Min-Jae Seo
, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Seung-Tak Ryu:
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. IEEE J. Solid State Circuits 55(10): 2660-2669 (2020)- 2019
- [j4]Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo, Mi-Young Kim, Min-Chul Shin, Seokjoon Kang, Junghyuk Yoon, Taek-Seung Kim, Seung-Tak Ryu:
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. IEEE J. Solid State Circuits 54(6): 1812-1823 (2019) - 2018
- [j3]Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim, Seung-Tak Ryu:
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3617-3627 (2018) - 2016
- [j2]Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs. IEEE J. Solid State Circuits 51(10): 2262-2273 (2016) - 2015
- [j1]Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Junho Cheon, Seung-Tak Ryu:
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. IEEE J. Solid State Circuits 50(10): 2431-2440 (2015)
Conference and Workshop Papers
- 2019
- [c3]Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, Seung-Tak Ryu:
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. A-SSCC 2019: 189-192 - 2015
- [c2]Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. A-SSCC 2015: 1-4 - 2014
- [c1]Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, Seung-Tak Ryu:
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. CICC 2014: 1-4
Coauthor Index
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