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ORCIDZhipeng Cao 0001
Person information
- affiliation: Information Engineering University, National Digital Switching System Engineering and Technological Research Center, China
- affiliation: People's Liberation Army Strategic Support Force, Institute of Information Technology
Other persons with the same name
- Zhipeng Cao — disambiguation page
- Zhipeng Cao 0002 — Tencent, T Lab, Beijing, China
- Zhipeng Cao 0003
![[0000-0002-8382-0033]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-8382-0033")
— Wuhan University, School of Remote Sensing and Information Engineering, China - Zhipeng Cao 0004 — Xuhui District Mental Health Center, Shanghai, China (and 2 more)
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2020 – today
- 2025
[j7]Zhipeng Cao, Qinrang Liu, Zhiquan Wan, Wenbo Zhang, Ke Song, Wenbin Liu:
Enhancing interconnection network topology for chiplet-based systems: An automated design framework. Future Gener. Comput. Syst. 163: 107547 (2025)- [j6]Zhipeng Cao, Bo Mei, Qinrang Liu, Xue Pei, Zhiquan Wan, Caining Wang:
MAHR: A Multi-Application Hybrid Reconfigurable Mechanism for Energy-Efficient Chiplet Interconnection Network. J. Circuits Syst. Comput. 34(1): 2550037:1-2550037:34 (2025) - [j5]Bo Mei, Wenbo Zhang, Zhipeng Cao, Wei Guo, Mingquan Zhang, Wenbin Liu, Zheng Du:
A Multi-Objective Task Mapping Method for Enhancing Security Against Hardware Trojans in Heterogeneous Multi-Core System. J. Circuits Syst. Comput. 34(6): 2550147:1-2550147:31 (2025) - [j4]Zhiquan Wan, Zhipeng Cao, Shunbin Li, Peijie Li, Qingwen Deng, Weihao Wang, Kun Zhang, Guandong Liu, Ruyun Zhang, Qinrang Liu:
Architectural Exploration for Waferscale Switching System. IEEE Trans. Very Large Scale Integr. Syst. 33(2): 512-524 (2025) - 2024
- [j3]Zhipeng Cao, Zhiquan Wan, Peijie Li, Qinrang Liu, Caining Wang, Yangxue Shao:
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems. Integr. 96: 102149 (2024) - [j2]Zhipeng Cao, Wei Guo, Zhiquan Wan, Peijie Li, Qinrang Liu, Caining Wang, Yangxue Shao:
ETRS: efficient turn restrictions setting method for boundary routers in chiplet-based systems. J. Supercomput. 80(14): 20488-20517 (2024) - [c1]Zhiquan Wan, Zhipeng Cao, Shunbin Li, Dehao Ye:
Modeling and Analysis of Waferscale Switching Network with Multiple System Faults. ISCAS 2024: 1-5 - 2021
- [j1]Zhipeng Cao, Qinrang Liu, Dongpei Liu, Yanbin Hu:
Enhanced System Design and Scheduling Strategy for Switches in Time-Sensitive Networking. IEEE Access 9: 42621-42634 (2021)
Coauthor Index
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