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Andres Viveros-Wacher

Andrés Viveros-Wacher

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Journal Articles

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2020
[j2]
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  - journals/tetc/Rangel-PatinoVR20
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  persistent URL:
  - https://dblp.org/rec/journals/tetc/Rangel-PatinoVR20
Francisco E. Rangel-Patino, Andres Viveros-Wacher, José Ernesto Rayas-Sánchez, Ismael Duron-Rosales, Edgar-Andrei Vega-Ochoa, Nagib Hakim, Enrique Lopez-Miralrio:
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. IEEE Trans. Emerg. Top. Comput. 8(2): 453-463 (2020)
2019
[j1]
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  - journals/tcad/Rangel-PatinoRV19
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  - https://dblp.org/rec/journals/tcad/Rangel-PatinoRV19
Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Andres Viveros-Wacher, José Luis Chavez-Hurtado, Edgar-Andrei Vega-Ochoa, Nagib Hakim:
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 733-740 (2019)

Conference and Workshop Papers

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2020
[c3]
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  - conf/itc/Sanchez-Martinez20
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  - https://dblp.org/rec/conf/itc/Sanchez-Martinez20
Cesar A. Sánchez-Martínez, Paulo López-Meyer, Esdras Juárez-Hernández, Aaron Desiga-Orenday, Andrés Viveros-Wacher:
High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques. ITC 2020: 1-5
2018
[c2]
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  - conf/lascas/Viveros-WacherB18
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Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Miguel A. Davalos-Santana, Edgar-Andrei Vega-Ochoa, José Ernesto Rayas-Sánchez:
Jitter tolerance acceleration using the golden section optimization technique. LASCAS 2018: 1-4
2014
[c1]
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  - conf/vts/Viveros-WacherAADMMV14
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Andres Viveros-Wacher, Ricardo Alejos, Liliana Alvarez, Israel Diaz-Castro, Brenda Marcial, Gaston Motola-Acuna, Edgar-Andrei Vega-Ochoa:
SMV methodology enhancements for high speed I/O links of SoCs. VTS 2014: 1-5

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