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Yavar Safaei Mehrabani
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2020 – today
- 2024
- [j13]Yavar Safaei Mehrabani
, Reza Faghih Mirzaee:
DAFA: Dynamic approximate full adders for high area and energy efficiency. Integr. 97: 102191 (2024) - 2022
- [j12]Yavar Safaei Mehrabani, Roghayeh Ataie, Mohammad Hossein Shafiabadi, Abolghasem Ghasempour:
Design and implementation of an ASIP for SHA-3 hash algorithm. Int. J. Inf. Comput. Secur. 17(3/4): 285-309 (2022) - [j11]Yavar Safaei Mehrabani
, Samaneh Goldani Gigasari
, Mohammad Mirzaei
, Hamidreza Uoosefian
:
A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology. ACM J. Emerg. Technol. Comput. Syst. 18(4): 74:1-74:20 (2022) - [j10]Akram Mohammadi, Mokhtar Mohammadi Ghanatghestani
, Amir Sabbagh Molahosseini, Yavar Safaei Mehrabani:
Image processing with high-speed and low-energy approximate arithmetic circuit. Sustain. Comput. Informatics Syst. 36: 100785 (2022) - 2021
- [j9]Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi
, Yavar Safaei Mehrabani
:
Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems. Microelectron. J. 108: 104962 (2021)
2010 – 2019
- 2017
- [j8]Yavar Safaei Mehrabani, Mohammad Hossein Shafiabadi:
A novel high-performance and reliable multi-threshold CNFET full adder cell design. Int. J. High Perform. Syst. Archit. 7(1): 15-25 (2017) - [j7]Yavar Safaei Mehrabani, Reza Faghih Mirzaee
, Zahra Zareei, Seyedeh Mohtaram Daryabari:
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector. J. Circuits Syst. Comput. 26(5): 1750082:1-1750082:15 (2017) - 2016
- [j6]Yavar Safaei Mehrabani
, Mohammad Eshghi:
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3268-3281 (2016) - 2015
- [j5]Yavar Safaei Mehrabani
, Mohammad Eshghi:
A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Circuits Syst. Signal Process. 34(3): 739-759 (2015) - [j4]Yavar Safaei Mehrabani
, Mohammad Eshghi:
Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Circuits Syst. Signal Process. 34(3): 761 (2015) - [j3]Yavar Safaei Mehrabani, Reza Faghih Mirzaee
, Mohammad Eshghi:
A novel low-energy CNFET-based full adder cell using pass-transistor logic. Int. J. High Perform. Syst. Archit. 5(4): 193-201 (2015) - [j2]Yavar Safaei Mehrabani, Mohammad Eshghi:
High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells. J. Circuits Syst. Comput. 24(9): 1550130:1-1550130:24 (2015) - 2013
- [j1]Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh:
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. Int. J. High Perform. Syst. Archit. 4(4): 196-203 (2013)
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