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Bahniman Ghosh
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2010 – 2019
- 2015
- [j22]Puneet Agrawal, Bahniman Ghosh:
Innovative design methodologies in quantum-dot cellular automata. Int. J. Circuit Theory Appl. 43(2): 253-262 (2015) - 2014
- [j21]Himanshu Gupta, Bahniman Ghosh:
Transistor size optimization in digital circuits using ant colony optimization for continuous domain. Int. J. Circuit Theory Appl. 42(6): 642-658 (2014) - [j20]Bahniman Ghosh, Jangam Siva Chandra, Akshay Kumar Salimath
:
Design of a Multi-Layered QCA Configurable Logic Block for FPGAs. J. Circuits Syst. Comput. 23(6) (2014) - [j19]Arun Kant Sharma, Shiva Asapu, Akshay Kumar Salimath
, Bahniman Ghosh:
Read and Write Analysis for Balanced Pattern Memristor Crossbar Array. J. Low Power Electron. 10(1): 84-87 (2014) - [j18]Bahniman Ghosh, Gaurav S. Solanki, Abhishek Banerjee:
Domain Wall Dynamics Due to Voltage Controlled Magnetic Anisotropy. J. Low Power Electron. 10(1): 88-91 (2014) - [j17]Bahniman Ghosh, Punyasloka Bal, Partha Mondal, M. W. Akram:
Device Physics of Germanium-Junctionless Tunnel Field Effect Transistor and an Approach to Optimize I on/I off by Drain Engineering and Work Function Engineering. J. Low Power Electron. 10(1): 92-100 (2014) - [j16]Bahniman Ghosh, Neelam Surana, M. W. Akram, Ball Mukund Mani Tripathi:
In0 25Ga0 75As Channel Double Gate Junctionless Transistor. J. Low Power Electron. 10(1): 101-106 (2014) - [j15]Bahniman Ghosh, A. Ajay:
2-Bit Full Adder Implementation Using Single Spin Logic Paradigm. J. Low Power Electron. 10(2): 214-219 (2014) - [j14]Jangam Siva Chandra, Kandula Suresh, Bahniman Ghosh:
Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design. J. Low Power Electron. 10(2): 272-278 (2014) - [j13]M. W. Akram, Bahniman Ghosh:
Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor. J. Low Power Electron. 10(2): 286-292 (2014) - [j12]Bahniman Ghosh, Partha Mondal, M. W. Akram, Punyasloka Bal:
Impact of High- Spacer on Junctionless Transistor in Sub-Threshold Regime. J. Low Power Electron. 10(2): 293-296 (2014) - [j11]Bahniman Ghosh, Abhinay Kumar:
Quantum-Dot Cellular Automata-Implementing Reversible Benchmarks. J. Low Power Electron. 10(3): 321-324 (2014) - [j10]Bahniman Ghosh, Shibir Basak, Pranav Kumar Asthana:
Performance Improvement in Nanoscale Ge-GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate. J. Low Power Electron. 10(3): 354-360 (2014) - [j9]Ankit Kumar Verma, Bahniman Ghosh, Bhaskar Awadhiya
, Tangudu Bharat Kumar:
Ab-Initio Modeling of Effect of Boron and Phosphorus Doping in CoFe/MgO Magnetic Tunnel Junctions. J. Low Power Electron. 10(3): 361-364 (2014) - [j8]Bahniman Ghosh, Aayush Gupta:
Spin Transport in Single Layer Germanene: The Role of Electron Electron Scattering. J. Low Power Electron. 10(3): 365-367 (2014) - [j7]Bahniman Ghosh, Aayush Gupta:
Effect of Nanoribbon Width and Strain on the Electronic Properties of the WS2 Nanoribbon. J. Low Power Electron. 10(3): 368-372 (2014) - [j6]Yuvaneet Bhaker, Princepreet Singh, Bahniman Ghosh:
Simulation of 2 Bit by 2 Bit Binary Multiplier Using Magnetic Tunnel Junction Device. J. Low Power Electron. 10(4): 580-583 (2014) - [j5]Shibir Basak, Bahniman Ghosh:
Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET. J. Low Power Electron. 10(4): 629-634 (2014) - [i1]Tangudu Bharat Kumar, Bhaskar Awadhiya, E. MeherAbhinav, Bahniman Ghosh, Bhupesh Bishnoi:
Performance Analysis of Spin Transfer Torque Random Access Memory with cross shaped free layer using Heusler Alloys by using micromagnetic studies. CoRR abs/1401.6971 (2014) - 2013
- [j4]Uzma Khan, Bahniman Ghosh, M. W. Akram:
Effect of Self Heating on Selective Buried Oxide and Silicon on Insulator Based Junctionless Transistors. J. Low Power Electron. 9(3): 295-301 (2013) - [j3]Bahniman Ghosh, Chandramauli Singh, Akshay Kumar Salimath
:
A Novel Approach of Full Adder and Arithmetic Logic Unit Design in Quantum Dot Cellular Automata. J. Low Power Electron. 9(4): 452-457 (2013) - [j2]Bahniman Ghosh, Uzma Khan, Ball Mukund Mani Tripathi, M. W. Akram:
Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors. J. Low Power Electron. 9(4): 490-495 (2013) - [j1]Yogesh Goswami, Ball Mukund Mani Tripathi, Pranav Kumar Asthana, Bahniman Ghosh:
Junctionless Tunnel Field Effect Transistor with Enhanced Performance Using III-V Semiconductor. J. Low Power Electron. 9(4): 496-500 (2013)
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