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Hasan Erdem Yantir
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2020 – today
- 2023
- [j11]Mohd. Tasleem Khan
, Hasan Erdem Yantir, Khaled Nabil Salama
, Ahmed M. Eltawil
:
Architectural Trade-Off Analysis for Accelerating LSTM Network Using Radix-r OBC Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 266-279 (2023) - [c9]Yunus Emre Eryilmaz, Hasan Erdem Yantir, Müstak E. Yalçin:
An Open-Source eFPGA-based SoC Design for Computation Acceleration. ICECS 2023: 1-4 - 2022
- [j10]Muhammad Irfan
, Hasan Erdem Yantir
, Zahid Ullah
, Ray C. C. Cheung:
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs. IEEE Embed. Syst. Lett. 14(2): 63-66 (2022) - [j9]Hasan Erdem Yantir
, Ahmed M. Eltawil
, Khaled N. Salama
:
A hardware/software co-design methodology for in-memory processors. J. Parallel Distributed Comput. 161: 63-71 (2022) - [j8]Mohammed E. Fouda
, Hasan Erdem Yantir
, Ahmed M. Eltawil
, Fadi J. Kurdahi
:
In-Memory Associative Processors: Tutorial, Potential, and Challenges. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2641-2647 (2022) - [j7]Wenzhe Guo
, Hasan Erdem Yantir
, Mohammed E. Fouda
, Ahmed M. Eltawil
, Khaled Nabil Salama
:
Toward the Optimal Design and FPGA Implementation of Spiking Neural Networks. IEEE Trans. Neural Networks Learn. Syst. 33(8): 3988-4002 (2022) - [i1]Mohammed E. Fouda, Hasan Erdem Yantir, Ahmed M. Eltawil
, Fadi J. Kurdahi:
In-memory Associative Processors: Tutorial, Potential, and Challenges. CoRR abs/2203.00662 (2022) - 2021
- [j6]Hasan Erdem Yantir
, Ahmed M. Eltawil
, Khaled N. Salama
:
IMCA: An Efficient In-Memory Convolution Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 447-460 (2021) - 2020
- [c8]Hasan Erdem Yantir, Ahmed M. Eltawil
, Khaled N. Salama
:
An Efficient 2D Discrete Cosine Transform Processor for Multimedia Applications. SIU 2020: 1-4
2010 – 2019
- 2019
- [j5]Rana A. Abdelaal
, Hasan Erdem Yantir
, Ahmed M. Eltawil
, Fadi J. Kurdahi
:
Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 302-312 (2019) - 2018
- [b1]Hasan Erdem Yantir:
Efficient Acceleration of Computation Using Associative In-memory Processing. University of California, Irvine, USA, 2018 - [j4]Hasan Erdem Yantir
, Ahmed M. Eltawil
, Fadi J. Kurdahi
:
A Hybrid Approximate Computing Approach for Associative In-Memory Processors. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 758-769 (2018) - [j3]Hasan Erdem Yantir
, Ahmed M. Eltawil
, Smaïl Niar, Fadi J. Kurdahi:
Power optimization techniques for associative processors. J. Syst. Archit. 90: 44-53 (2018) - [j2]Hasan Erdem Yantir
, Ahmed M. Eltawil
, Fadi J. Kurdahi
:
A Two-Dimensional Associative Processor. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1659-1670 (2018) - [c7]Mohamed Ayoub Neggaz, Hasan Erdem Yantir, Smaïl Niar, Ahmed M. Eltawil
, Fadi J. Kurdahi:
Rapid in-memory matrix multiplication using associative processor. DATE 2018: 985-990 - [c6]Hasan Erdem Yantir, Ahmed M. Eltawil
, Fadi J. Kurdahi:
Low-Power Resistive Associative Processor Implementation Through the Multi-Compare. ICECS 2018: 165-168 - 2017
- [j1]Hasan Erdem Yantir, Ahmed M. Eltawil
, Fadi J. Kurdahi
:
Approximate Memristive In-memory Computing. ACM Trans. Embed. Comput. Syst. 16(5s): 129:1-129:18 (2017) - [c5]Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil
, Fadi J. Kurdahi
:
Efficient pulsed-latch implementation for multiport register files: work-in-progress. CASES 2017: 5:1-5:2 - 2016
- [c4]Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil
, Fadi J. Kurdahi
:
Process variations-aware resistive associative processor design. ICCD 2016: 49-55 - 2014
- [c3]Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smaïl Niar:
Application specific multi-port memory customization in FPGAs. FPL 2014: 1-4 - [c2]Hasan Erdem Yantir, Arda Yurdakul:
An Efficient Heterogeneous Register File Implementation for FPGAs. IPDPS Workshops 2014: 293-298 - 2013
- [c1]Hasan Erdem Yantir, Salih Bayar
, Arda Yurdakul:
Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs. DSD 2013: 185-192
Coauthor Index
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